Role - SoC Design Engineer

Location - Toronto, ON ( Hybrid )

An RTL design and integration role in our System on Chip (SoC) design team, where numerous subsystems and IP cores are integrated to produce high performance SoC products. Our designers work on SoC level RTL design, block level RTL design, and/or subsystem level integration for a variety of SoC products. Your expertise will be deployed in SoC ASIC projects targeting networking, security, storage, and other applications.

Experienced RTL designer who has a passion for modern digital ASIC design. You are a team player who has excellent written and verbal communication skills with experience collaborating across multiple design sites and time zones. You have strong analytical and problem-solving skills and enjoy tackling new challenges. You pay attention to details. You enjoy working amongst a multi-disciplinary team of professionals with diverse skills and experiences to complete projects in an efficient manner.

Key Responsibilities

Develop and maintain SoC and subsystems synthesizable RTL, design methodology and infrastructure
Collaborate directly with IP Architecture, SoC Architecture and Design Leads
Debug and resolve issues with SoC Integration, SoC Design Verification and post-silicon validation teams
Work with IP development teams and Physical Design (PD) team to meet SoC Power/Performance/Area goals by providing synthesis and timing closure support
Resolve SoC simulation regression failures through close collaboration with SoC Verification Team and working with Verification Team members to ensure achievement of verification quality metrics
Support the activities of the Emulation Team
Attend and contribute to regular technical status meetings

Experience

Experienced RTL (Verilog / System Verilog) ASIC design experience through implementations targeting leading edge ASIC technologies
Proven experience with industry-leading ASIC design tools, synthesis tools, flows, and timing closure
Experience executing design checks such as lint, CDC, and LEC using industry standard ASIC tools
Familiarity with industry standard power flows
Proficient with scripting languages such as Python, Perl, TCL, Makefile, and csh/bash
Skilled in simulation and debugging with functional verification tools from Synopsys, Cadence, and/or Siemens (Mentor) including Gate-level simulations
Industry experience with ASIC SoC design and integration
Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
Experience in modern, complex networking architecture and digital design in general
Familiarity with networking protocols (such as Ethernet) and standards for digital communication systems, optical communications, and packet processing applications
Familiarity with encryption protocols (such as MACsec and IPsec) and security technologies for digital communication systems

Academic Credentials

Bachelors or Masters degree in Computer/Electrical Engineering