SoC Static Timing Analysis (STA) Engineer

• MARKHAM, Canada
• Engineering
• 69787
• CAD $124,000.00/Yr.
• CAD $186,000.00/Yr.

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

THE ROLE:
AMD is seeking an ASIC Design STA Engineer to support the development of large SoCs featuring multiple physical blocks and over 300 clock domains. The candidate will be responsible for building and verifying timing constraints for complex SoC designs. This role requires strong expertise in SDC (Synopsys Design Constraints), proficiency with EDA tools, and TCL scripting skills. The ideal candidate will have extensive experience in developing and debugging timing constraints, improving RTL quality metrics for hierarchical designs, and automating these processes to increase efficiency. Familiarity with both front-end (RTL) and back-end (Synthesis and P&R) design flows is preferred.

THE PERSON:
We are looking for high-energy candidates with strong written and verbal communication skills, structured and well-organized work habits, and a team- and goal-oriented mindset.

KEY RESPONSIBILITIES:

• Develop complex multi-mode/multi-corner timing DFT constraints (SDC) compatible with RTL and signoff flows.
• Implement pre-route timing checks and QoR cleanup to eliminate timing constraint issues and ensure quality handoff for STA checks.
• Collaborate with CAD teams to develop pre-production synthesis (Design Compiler) and STA (PrimeTime) workflows.
• Utilize expertise in SDC, EDA tools, and Tcl scripting (both in EDA environments and standalone Linux Tcl shells).
• Continuously review and improve processes for early issue detection during the design phase.

PREFERRED EXPERIENCE:

• Hands-on experience building timing constraints for IPs, blocks, and full-chip implementations in flat and hierarchical flows.
• Proficient in analyzing timing reports and identifying design and constraint-related issues.
• Solid understanding of timing analysis methodologies.
• Ability to multitask and quickly learn new flows, tools, and concepts.
• Experience improving methodologies and automation.
• Preferred EDA tool experience: Synopsys Design Compiler, PrimeTime, GCA, Spyglass, Fishtail, etc.
• Proven track record developing complex TCL scripts for Synopsys DC and PT environments.
• Experience writing custom TCL QC and QoR checks using DC/PT object attribute queries and filters.
• Strong analytical and problem-solving skills.
• Backend design experience (P&R, CTS, etc.) is a plus.
• Knowledge of DFT methodologies is preferred.
• Prior experience with tape-out and timing constraint sign-off is highly desirable.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.

LOCATION:

• Markham, Ontario

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.