Senior FPGA Design Engineer, RTL to Timing Closure
About the role
USD 85 to 110 per hour, roughly USD 170,000 to 220,000 annualized at full utilization, ben…SystemVerilogUVM testbench architectureFunctional and code coverage closureSystemVerilog Assertions (SVA)Constrained random verificationVCS, Xcelium, or QuestaUSD 80 to 120 per hour, approximately USD 160,000 to 240,000 annualized at full utilizatio…SystemVerilog or VHDLVivado or QuartusTiming closure and SDC/XDC constraintsClock domain crossing designPCIe, Ethernet, or DDR interfacesOn chip debug (ILA or Signal Tap)USD 75 to 100 per hour, approximately USD 150,000 to 200,000 annualized at full utilizatio…SystemVerilog RTL designMicroarchitecture specificationLint and CDC signoff (SpyGlass or similar)Synthesis and static timing (Design Compiler or Genus)AMBA AXI, AHB, or APB integrationLow power design intent (UPF)
Not the right fit? Search for FPGA Design Engineer, RTL to Timing Closure jobs in Toronto, Ontario, Canada
About ShawSilicon
The semiconductor industry will be short 67,000 engineers by 2030. The CHIPS Act is injecting $52 billion into domestic manufacturing. Intel, TSMC, and Samsung are building fabs across North America. Demand for hardware engineers is exploding. Supply isn't keeping up. And generalist recruiters can't solve a specialist problem. ShawSilicon is the first talent marketplace built exclusively for semiconductor engineers - by semiconductor engineers. Founded by a highly skilled, award-winning FPGA design veteran who spent his career watching brilliant hardware teams held back by empty chairs, ShawSilicon solves the two biggest problems in semiconductor hiring: For companies: finding candidates who can actually do the work - not resume-padding generalists who "know Verilog" from one university course. Every engineer on our platform is technically vetted by engineers with real tapeout experience. We match you with candidates in under 24 hours at rates 30-50% below traditional staffing agencies. For engineers: getting seen by the right companies without competing against thousands of software developers on generic platforms. We put your hardware expertise front and center and match you with companies that value what you actually do. Our specializations: → FPGA Design (Xilinx/AMD, Intel, Lattice) → ASIC Design & RTL Development → Verification & DV (UVM, Formal, CDC) → Physical Design & Place-and-Route → Analog & Mixed-Signal IC Design → Embedded Hardware Systems → AI/ML Chip Architecture → DFT & Design for Manufacturing We're currently onboarding our founding 200 companies and 200 engineers. Founding members receive priority access and permanently locked pricing. Hiring hardware talent? → shawsilicon.ai Are hardware talent? → shawsilicon.ai 📩 sales@shawsilicon.ai
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Senior FPGA Design Engineer, RTL to Timing Closure
About the role
USD 85 to 110 per hour, roughly USD 170,000 to 220,000 annualized at full utilization, ben…SystemVerilogUVM testbench architectureFunctional and code coverage closureSystemVerilog Assertions (SVA)Constrained random verificationVCS, Xcelium, or QuestaUSD 80 to 120 per hour, approximately USD 160,000 to 240,000 annualized at full utilizatio…SystemVerilog or VHDLVivado or QuartusTiming closure and SDC/XDC constraintsClock domain crossing designPCIe, Ethernet, or DDR interfacesOn chip debug (ILA or Signal Tap)USD 75 to 100 per hour, approximately USD 150,000 to 200,000 annualized at full utilizatio…SystemVerilog RTL designMicroarchitecture specificationLint and CDC signoff (SpyGlass or similar)Synthesis and static timing (Design Compiler or Genus)AMBA AXI, AHB, or APB integrationLow power design intent (UPF)
Not the right fit? Search for FPGA Design Engineer, RTL to Timing Closure jobs in Toronto, Ontario, Canada
About ShawSilicon
The semiconductor industry will be short 67,000 engineers by 2030. The CHIPS Act is injecting $52 billion into domestic manufacturing. Intel, TSMC, and Samsung are building fabs across North America. Demand for hardware engineers is exploding. Supply isn't keeping up. And generalist recruiters can't solve a specialist problem. ShawSilicon is the first talent marketplace built exclusively for semiconductor engineers - by semiconductor engineers. Founded by a highly skilled, award-winning FPGA design veteran who spent his career watching brilliant hardware teams held back by empty chairs, ShawSilicon solves the two biggest problems in semiconductor hiring: For companies: finding candidates who can actually do the work - not resume-padding generalists who "know Verilog" from one university course. Every engineer on our platform is technically vetted by engineers with real tapeout experience. We match you with candidates in under 24 hours at rates 30-50% below traditional staffing agencies. For engineers: getting seen by the right companies without competing against thousands of software developers on generic platforms. We put your hardware expertise front and center and match you with companies that value what you actually do. Our specializations: → FPGA Design (Xilinx/AMD, Intel, Lattice) → ASIC Design & RTL Development → Verification & DV (UVM, Formal, CDC) → Physical Design & Place-and-Route → Analog & Mixed-Signal IC Design → Embedded Hardware Systems → AI/ML Chip Architecture → DFT & Design for Manufacturing We're currently onboarding our founding 200 companies and 200 engineers. Founding members receive priority access and permanently locked pricing. Hiring hardware talent? → shawsilicon.ai Are hardware talent? → shawsilicon.ai 📩 sales@shawsilicon.ai