About the role
- Join the leading chiplet startup
- As an Eliyan Staff Digital Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility
- In this role you will lead the frontend design of our D2D PHY - the core tech behind NuLink, our chiplet interconnect platform
- You’ll own the digital PHY from microarchitecture through synthesis, working closely with our architecture, analog, verification, and physical design teams
- This is a hands-on technical leadership role
- You’ll define PHY architecture, write RTL, optimize for synthesis, create timing constraints, develop firmware sequences, and ensure clean integration across the stack
- Your work directly enables next-gen chiplet-based AI and HPC systems
- We offer a fun work environment with excellent benefits
- Own D2D PHY digital design from microarchitecture definition through synthesis and PD handoff
- Design data path and clocking architecture for UCIe-compliant advanced package PHY
- Write RTL for link training, calibration engines, rate adaptation, CDC, FIFO alignment, and lane deskew
- Create microarchitecture specs with power analysis, latency metrics, and performance characterization
- Make architectural trade-offs balancing performance, power, area, and timing
- Drive synthesis optimization: area, timing, power, QoR
- Create comprehensive SDC constraints for multi-clock domains, false paths, multi-cycle paths, CDC
- Generate UPF power specifications with voltage domains, isolation, and retention
- Establish LINT/CDC flows with rulesets and waiver management
- Deliver synthesis-ready netlists with handoff documentation for physical design
- Coordinate with analog PHY team on digital control for TX/RX, PLL, calibration
- Partner with verification team on testbench requirements, coverage goals, and protocol compliance
- Collaborate with physical design on placement guidelines, clock tree requirements, routing constraints
- Work with firmware team on register interfaces, link training sequences, runtime control
- Mentor 2-3 digital designers on frontend design and synthesis optimization
- Drive design reviews and technical decisions across teams- Advanced CDC design, link training protocols, elastic buffer architectures
- 8+ years digital frontend design with 4+ years in PHY or high-speed interfaces
- Strong understanding of UCIe or other high-speed interfaces like DDR/Serdes
- Expert SystemVerilog RTL design with strong synthesis optimization skills
- 3+ successful tapeouts as design lead in advanced nodes (7nm or below)
- Hands-on with synthesis tools (Synopsys DC/Fusion Compiler or Cadence Genus)
- Deep expertise in D2D PHY, DDR PHY, or SerDes digital design
- Experience with SDC constraints, UPF, STA methodology
- Proven ability to lead frontend design and coordinate across teams
- 12+ years with demonstrated technical leadership
- UCIe PHY design or certification experience
- SerDes digital control (TX/RX equalization, CDR), PCIe PHY, or CXL PHY experience
- DDR4/DDR5/LPDDR PHY or DFI interface experience
- Advanced packaging knowledge: 2.5D, 3D, organic substrate
- Firmware development for PHY control or low-level driver implementation
- Publications or patents in PHY design
- Python/Perl/Tcl scripting for design automation
Not the right fit? Search for Digital Design Engineer jobs in Bay Area, Vancouver or Toronto
Similar Jobs
About the role
- Join the leading chiplet startup
- As an Eliyan Staff Digital Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility
- In this role you will lead the frontend design of our D2D PHY - the core tech behind NuLink, our chiplet interconnect platform
- You’ll own the digital PHY from microarchitecture through synthesis, working closely with our architecture, analog, verification, and physical design teams
- This is a hands-on technical leadership role
- You’ll define PHY architecture, write RTL, optimize for synthesis, create timing constraints, develop firmware sequences, and ensure clean integration across the stack
- Your work directly enables next-gen chiplet-based AI and HPC systems
- We offer a fun work environment with excellent benefits
- Own D2D PHY digital design from microarchitecture definition through synthesis and PD handoff
- Design data path and clocking architecture for UCIe-compliant advanced package PHY
- Write RTL for link training, calibration engines, rate adaptation, CDC, FIFO alignment, and lane deskew
- Create microarchitecture specs with power analysis, latency metrics, and performance characterization
- Make architectural trade-offs balancing performance, power, area, and timing
- Drive synthesis optimization: area, timing, power, QoR
- Create comprehensive SDC constraints for multi-clock domains, false paths, multi-cycle paths, CDC
- Generate UPF power specifications with voltage domains, isolation, and retention
- Establish LINT/CDC flows with rulesets and waiver management
- Deliver synthesis-ready netlists with handoff documentation for physical design
- Coordinate with analog PHY team on digital control for TX/RX, PLL, calibration
- Partner with verification team on testbench requirements, coverage goals, and protocol compliance
- Collaborate with physical design on placement guidelines, clock tree requirements, routing constraints
- Work with firmware team on register interfaces, link training sequences, runtime control
- Mentor 2-3 digital designers on frontend design and synthesis optimization
- Drive design reviews and technical decisions across teams- Advanced CDC design, link training protocols, elastic buffer architectures
- 8+ years digital frontend design with 4+ years in PHY or high-speed interfaces
- Strong understanding of UCIe or other high-speed interfaces like DDR/Serdes
- Expert SystemVerilog RTL design with strong synthesis optimization skills
- 3+ successful tapeouts as design lead in advanced nodes (7nm or below)
- Hands-on with synthesis tools (Synopsys DC/Fusion Compiler or Cadence Genus)
- Deep expertise in D2D PHY, DDR PHY, or SerDes digital design
- Experience with SDC constraints, UPF, STA methodology
- Proven ability to lead frontend design and coordinate across teams
- 12+ years with demonstrated technical leadership
- UCIe PHY design or certification experience
- SerDes digital control (TX/RX equalization, CDR), PCIe PHY, or CXL PHY experience
- DDR4/DDR5/LPDDR PHY or DFI interface experience
- Advanced packaging knowledge: 2.5D, 3D, organic substrate
- Firmware development for PHY control or low-level driver implementation
- Publications or patents in PHY design
- Python/Perl/Tcl scripting for design automation
Not the right fit? Search for Digital Design Engineer jobs in Bay Area, Vancouver or Toronto