Senior Principal SOC Power Lead
About the role
Job Overview
We are seeking an experienced Senior Principal SoC Power Lead to drive power analysis, modeling, and optimization for advanced System-on-Chip (SoC) solutions. This role will lead a team of power engineers responsible for pre- and post-silicon power convergence, working closely with architecture, design, verification, and product teams to deliver best-in-class power efficiency. The ideal candidate will bring deep expertise in power analysis methodologies, SoC lifecycle flows, and cross-functional collaboration from architecture definition through productization.
Responsibilities:
- Lead SoC power analysis, modeling, and performance-per-watt optimization initiatives
- Drive power convergence across pre-silicon and post-silicon phases
- Collaborate with architecture, design, verification, and product teams to meet performance and power targets
- Develop and refine power modeling methodologies and workflows to improve accuracy, turnaround time, and silicon correlation
- Promote innovation and continuous improvement in power attainment strategies
- Plan and execute projects across multiple teams while mentoring junior engineers
Required Skills & Experience
- Strong technical leadership with the ability to drive complex, multi-team projects
- Expertise in RTL and netlist-based power analysis and sign-off flows
- Solid understanding of EDA tools and SoC physical design trends
Knowledge of ASIC design dependencies impacting power efficiency, including:
- Technology nodes
- Mixed-Vt design
- Standard cell and memory library selection
- Voltage and power domain partitioning
- Experience driving multiple SoC programs and mentoring engineers
Verification experience creating workload using simulation/emulation platforms such as:
- VCS
- Questasim
- Incisive
- Veloce Strato
- Palladium
- Zebu
Nice to Have
- Understanding of software use-cases, benchmarks, and workload interaction with hardware low-power features such as:
- Clock and power gating
- Voltage and frequency scaling
- Memory and logic retention
- Python for automation and power modeling
- Experience decomposing SoC use-case power budgets into IP-level power targets
About Chiparama
Chiparama: Your Global Partner for ASIC & SOC Design
At Chiparama (www.chiparama.com), we specialize in delivering cutting-edge ASIC and SOC design solutions. Our team of experienced engineers is dedicated to turning complex ideas into silicon reality.
Our Core Services:
Architectural Design: System-level modeling and simulation Power, Performance, and Area (PPA) optimization RTL Design & Verification: VHDL/Verilog coding and synthesis Formal verification and static timing analysis Advanced verification methodologies (UVM, OVM) Physical Design & Layout: Floorplanning, placement, and routing Clock tree synthesis and power integrity analysis Post-Silicon Validation & Testing: Silicon bring-up and debug Performance characterization and functional testing Advanced Technologies & Design Services:
Low Power Design: Optimize power consumption with techniques like power gating and DVFS. High-Speed Interface Design: Implement high-speed interfaces like PCIe, USB, and DDR. IP Integration & Management: Seamlessly integrate third-party IP into your design. Process Migration: Ensure smooth technology transitions to stay ahead of the curve.
Why Choose Chiparama?
Global Reach: We collaborate with clients worldwide. Expert Team: Our engineers have a proven track record of success. Customized Solutions: We tailor our services to meet your specific needs. Quality Commitment: We deliver exceptional results and exceed expectations. State-of-the-Art Tools and Technologies: We leverage the latest industry tools to ensure optimal results.
Contact us today to discuss your next project and let's innovate together.
Senior Principal SOC Power Lead
About the role
Job Overview
We are seeking an experienced Senior Principal SoC Power Lead to drive power analysis, modeling, and optimization for advanced System-on-Chip (SoC) solutions. This role will lead a team of power engineers responsible for pre- and post-silicon power convergence, working closely with architecture, design, verification, and product teams to deliver best-in-class power efficiency. The ideal candidate will bring deep expertise in power analysis methodologies, SoC lifecycle flows, and cross-functional collaboration from architecture definition through productization.
Responsibilities:
- Lead SoC power analysis, modeling, and performance-per-watt optimization initiatives
- Drive power convergence across pre-silicon and post-silicon phases
- Collaborate with architecture, design, verification, and product teams to meet performance and power targets
- Develop and refine power modeling methodologies and workflows to improve accuracy, turnaround time, and silicon correlation
- Promote innovation and continuous improvement in power attainment strategies
- Plan and execute projects across multiple teams while mentoring junior engineers
Required Skills & Experience
- Strong technical leadership with the ability to drive complex, multi-team projects
- Expertise in RTL and netlist-based power analysis and sign-off flows
- Solid understanding of EDA tools and SoC physical design trends
Knowledge of ASIC design dependencies impacting power efficiency, including:
- Technology nodes
- Mixed-Vt design
- Standard cell and memory library selection
- Voltage and power domain partitioning
- Experience driving multiple SoC programs and mentoring engineers
Verification experience creating workload using simulation/emulation platforms such as:
- VCS
- Questasim
- Incisive
- Veloce Strato
- Palladium
- Zebu
Nice to Have
- Understanding of software use-cases, benchmarks, and workload interaction with hardware low-power features such as:
- Clock and power gating
- Voltage and frequency scaling
- Memory and logic retention
- Python for automation and power modeling
- Experience decomposing SoC use-case power budgets into IP-level power targets
About Chiparama
Chiparama: Your Global Partner for ASIC & SOC Design
At Chiparama (www.chiparama.com), we specialize in delivering cutting-edge ASIC and SOC design solutions. Our team of experienced engineers is dedicated to turning complex ideas into silicon reality.
Our Core Services:
Architectural Design: System-level modeling and simulation Power, Performance, and Area (PPA) optimization RTL Design & Verification: VHDL/Verilog coding and synthesis Formal verification and static timing analysis Advanced verification methodologies (UVM, OVM) Physical Design & Layout: Floorplanning, placement, and routing Clock tree synthesis and power integrity analysis Post-Silicon Validation & Testing: Silicon bring-up and debug Performance characterization and functional testing Advanced Technologies & Design Services:
Low Power Design: Optimize power consumption with techniques like power gating and DVFS. High-Speed Interface Design: Implement high-speed interfaces like PCIe, USB, and DDR. IP Integration & Management: Seamlessly integrate third-party IP into your design. Process Migration: Ensure smooth technology transitions to stay ahead of the curve.
Why Choose Chiparama?
Global Reach: We collaborate with clients worldwide. Expert Team: Our engineers have a proven track record of success. Customized Solutions: We tailor our services to meet your specific needs. Quality Commitment: We deliver exceptional results and exceed expectations. State-of-the-Art Tools and Technologies: We leverage the latest industry tools to ensure optimal results.
Contact us today to discuss your next project and let's innovate together.