About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

This is an existing vacancy.

Your Team, Your Impact

Marvell's Advanced Technology team is seeking a Principal SI/PI Engineer to provide silicon‑level technical leadership for high‑speed wireline and optical interface designs, including SerDes, die‑to‑die, optical DSP interfaces, and electrical‑to‑optical interconnects. This role focuses on on‑die signal and power integrity, from architecture through silicon validation, and influences next‑generation Marvell wireline and optical platforms.

What You Can Expect

• Serve as silicon SI/PI technical authority across wireline and optical interface IP and SoCs.
• Define on‑die channel and power delivery architectures for high‑speed IO and optical interfaces.
• Influence SerDes and IO specifications, including jitter/noise budgets, equalization strategy, and PI targets.

Signal Integrity (Silicon Focus)

• Lead SI analysis for NRZ and PAM4 SerDes (56G/112G/224G+).
• Perform channel modeling, S‑parameter analysis, eye/jitter/BER analysis, and sensitivity to on‑die parasitics.
• Work closely with analog/mixed‑signal designers to optimize TX/RX architectures and robustness.

Optical & Electro‑Optical Interfaces

• Drive SI for electrical interfaces into optical systems, including optical DSP IO and modulator drivers.
• Analyze jitter and noise transfer from electrical SerDes into optical modulation.
• Correlate electrical SI metrics with optical link margin and performance.

Power Integrity

• Architect and analyze on‑die and near‑die PDN for high‑speed interfaces.
• Define impedance targets and mitigate SSN, supply‑induced jitter, and noise coupling.
• Drive PI‑aware IO and floorplanning decisions.

Silicon Bring‑Up & Methodology

• Correlate simulations with silicon measurements (eye, jitter, noise).
• Support first‑silicon bring‑up, debug, and root‑cause analysis.
• Establish SI/PI sign‑off criteria and best practices across design teams.

What We're Looking For

• MS or PhD in Electrical Engineering or related field.
• 10+ years of experience in SI/PI for high‑speed silicon wireline interfaces.
• Deep expertise in high‑speed SerDes architectures, including NRZ and PAM4 signaling, jitter decomposition, and noise analysis.
• Strong power integrity background, including:
  • On‑die and near‑die PDN architecture
  • Impedance target definition and frequency‑domain analysis
  • Simultaneous switching noise (SSN) and supply‑induced jitter mitigation
  • Supply noise coupling into sensitive SerDes and optical interface circuits
• Proven experience with on‑die channel modeling and S‑parameter analysis.
• Experience analyzing electrical interfaces for optical systems (optical DSP IO, modulator drivers, or electro‑optic interfaces).
• Hands‑on experience with industry tools such as Cadence Sigrity, Keysight ADS / SIPro, and Ansys HFSS (or equivalent).
• Strong understanding of CMOS mixed‑signal design, high‑speed IO circuits, and silicon‑level noise coupling mechanisms.
• Demonstrated ability to lead technically across silicon design teams and influence architecture and sign‑off decisions.

Expected Base Pay Range (CAD)

164,000 - 218,700, $ per annum

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our

Careers

page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Marvell may employ artificial intelligence technologies to assist in the evaluation of job applications. All application reviews include meaningful human involvement, and no hiring decisions are made solely on the basis of automated processing.

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