ASIC Design Verification (DV) Engineer – UVM / PCIe / UCIe / Ethernet

Location: Remote (US – EST Time Zone) Employment Type: Contract Experience: 5+ Years

Mandatory Skills

ASIC Design Verification SystemVerilog UVM (Universal Verification Methodology) PCIe UCIe 2.0 Ethernet Protocol Verification Functional Verification Test Development Debugging Coverage Closure

Preferred Skills

ASIC Switch/NIC Verification Verification Planning Assertions (SVA) Functional Coverage Regression Testing Simulation & Debug Tools

Key Responsibilities

Own the verification of 4–5 ASIC design blocks independently. Develop and maintain UVM-based verification environments, sequences, and test cases. Perform functional verification using SystemVerilog/UVM methodologies. Verify ASIC designs supporting PCIe, UCIe 2.0, and Ethernet protocols. Develop and execute verification plans, test scenarios, and regression suites. Debug simulation failures and resolve functional issues. Drive functional coverage collection, analysis, and closure. Collaborate with design engineers to identify and resolve design issues. Deliver end-to-end verification for assigned ASIC blocks. Work closely with customer teams operating in the US EST time zone. Utilize the customer-provided verification infrastructure and testbench environment.

Required Experience

5+ years of experience in ASIC Design Verification. Strong hands-on experience with SystemVerilog and UVM. Experience verifying high-speed interfaces such as PCIe, UCIe 2.0, and Ethernet. Strong debugging and functional verification skills. Experience creating verification environments, sequences, and test cases. Hands-on experience with coverage-driven verification and coverage closure. Ability to independently own verification deliverables for multiple design blocks. Strong analytical, debugging, and problem-solving skills. Excellent communication skills and ability to collaborate with distributed engineering teams.