STA & Timing Methodology Engineer (Senior Staff)
Top Benefits
About the role
The Opportunity We're looking for the Wavemakers of tomorrow.
Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.
What you’ll do
- Own STA sign-off for complex ASICs/SoCs: drive MCMM timing closure across all PVT corners and modes (functional & test), meeting performance, power, and schedule targets.
- Set the timing methodology: define MMMC views, library/RC corner strategy, OCV/AOCV/POCV/LVF derates, CPPR, PBA vs GBA usage, SI/crosstalk/noise handling, waveform propagation, and aging/IR-aware considerations.
- Build bullet-proof constraints (SDC): clocks & generated clocks, clock groups, exceptions (false/multicycle/min/max), interface and hierarchical constraints, and low-power/UPF mode handling.
- Lead timing closure with PD & synthesis: craft ECO strategies (sizing, buffering, Vt swaps, useful skew), align CTS/route levers with clear QoR targets, and validate with path-based analysis.
- Automate at scale: develop Python/Tcl tools for constraint generation/validation, report parsing, dashboards, and regressions; introduce and productionize AI/agent workflows to triage violations, classify root-causes, and recommend ECOs.
- Partner cross-functionally with RTL, PD, AMS, DFT, and verification teams to resolve issues at digital/analog boundaries and in test modes.
- Guide equivalence & ECOs: use FM/LEC to validate synthesis and post-ECO logic changes.
- Lead & mentor a small team of STA engineers; run reviews, establish best practices/checklists, and communicate status, risks, and decisions to stakeholders and leadership.
- Continuously improve: track tool/foundry/industry advances and evolve our methodology—especially around AI-assisted flows.
What you’ll need
-
BS/MS in EE/CE (or equivalent).
-
8–12+ years owning STA sign-off and timing closure on large, advanced-node ASICs/SoCs.
-
Expert STA depth:
-
SDC authoring and hierarchical STA for MCMM sign-off
-
Variation & derates (OCV/AOCV/POCV, LVF), CPPR, PBA, SI/crosstalk/noise
-
Clocking/CTS constraints, CDC interfaces, test/scan mode timing
-
Hands-on ECO closure with strong understanding of PnR levers
-
Tool proficiency: PrimeTime and/or Tempus; exposure to synthesis (Design Compiler/Fusion) and PnR (Innovus/ICC2) environments.
-
Strong automation skills: Tcl and Python for robust, maintainable flow tooling and data analysis.
-
AI mindset: demonstrable enthusiasm for—ideally experience with—integrating LLM/agent-based tools into EDA flows (e.g., violation triage, log intelligence, fix suggestions, experiment tracking).
-
Communication & leadership: ability to mentor, influence across functions, and present complex findings clearly.
Nice to have
- Experience with UPF/CPF low-power timing, IR/EM-aware timing, statistical/SSTA concepts, and LVF sigma usage.
- Mixed-signal/PHY boundary timing (e.g., DDR, PCIe, SerDes).
- Data pipeline skills (dashboards, databases) and/or scaling regressions on cloud/HPC.
We have a flexible work environment to support and help employees thrive in personal and professional capacities. You’ll also be eligible for competitive benefits described as per below: Health & Wellness Our programs emphasize knowledge and prevention, helping you stay proactive and prepared to manage your health at every stage.
- Comprehensive health plan
- Health Spending Account (HSA)
- Wellness Spending Account (WSA)
- Employee Assistance Program (EAP)
Time Off We value the importance of rest and recharge, which is why we offer flexible time off options to support your well-being.
- Paid Vacation
- Paid Holidays
- Parental Leave Top-Up Program
Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.
About Alphawave Semi
We work to create silicon that enables the highest performing, most reliable and lowest power digital communication networks.
Alphawave Semi is a global leader in high-speed connectivity for the world’s technology infrastructure. Faced with the exponential growth of data, Alphawave Semi’s technology services a critical need: Enabling data to travel faster, more reliably and with higher performance at lower power.
We are a vertically integrated semiconductor company, and our IP, custom silicon, and connectivity products are deployed by global tier-one customers in data centers, compute, networking, AI, 5G, autonomous vehicles, and storage. Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, our mission is to accelerate the critical data infrastructure at the heart of our digital world.
STA & Timing Methodology Engineer (Senior Staff)
Top Benefits
About the role
The Opportunity We're looking for the Wavemakers of tomorrow.
Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.
What you’ll do
- Own STA sign-off for complex ASICs/SoCs: drive MCMM timing closure across all PVT corners and modes (functional & test), meeting performance, power, and schedule targets.
- Set the timing methodology: define MMMC views, library/RC corner strategy, OCV/AOCV/POCV/LVF derates, CPPR, PBA vs GBA usage, SI/crosstalk/noise handling, waveform propagation, and aging/IR-aware considerations.
- Build bullet-proof constraints (SDC): clocks & generated clocks, clock groups, exceptions (false/multicycle/min/max), interface and hierarchical constraints, and low-power/UPF mode handling.
- Lead timing closure with PD & synthesis: craft ECO strategies (sizing, buffering, Vt swaps, useful skew), align CTS/route levers with clear QoR targets, and validate with path-based analysis.
- Automate at scale: develop Python/Tcl tools for constraint generation/validation, report parsing, dashboards, and regressions; introduce and productionize AI/agent workflows to triage violations, classify root-causes, and recommend ECOs.
- Partner cross-functionally with RTL, PD, AMS, DFT, and verification teams to resolve issues at digital/analog boundaries and in test modes.
- Guide equivalence & ECOs: use FM/LEC to validate synthesis and post-ECO logic changes.
- Lead & mentor a small team of STA engineers; run reviews, establish best practices/checklists, and communicate status, risks, and decisions to stakeholders and leadership.
- Continuously improve: track tool/foundry/industry advances and evolve our methodology—especially around AI-assisted flows.
What you’ll need
-
BS/MS in EE/CE (or equivalent).
-
8–12+ years owning STA sign-off and timing closure on large, advanced-node ASICs/SoCs.
-
Expert STA depth:
-
SDC authoring and hierarchical STA for MCMM sign-off
-
Variation & derates (OCV/AOCV/POCV, LVF), CPPR, PBA, SI/crosstalk/noise
-
Clocking/CTS constraints, CDC interfaces, test/scan mode timing
-
Hands-on ECO closure with strong understanding of PnR levers
-
Tool proficiency: PrimeTime and/or Tempus; exposure to synthesis (Design Compiler/Fusion) and PnR (Innovus/ICC2) environments.
-
Strong automation skills: Tcl and Python for robust, maintainable flow tooling and data analysis.
-
AI mindset: demonstrable enthusiasm for—ideally experience with—integrating LLM/agent-based tools into EDA flows (e.g., violation triage, log intelligence, fix suggestions, experiment tracking).
-
Communication & leadership: ability to mentor, influence across functions, and present complex findings clearly.
Nice to have
- Experience with UPF/CPF low-power timing, IR/EM-aware timing, statistical/SSTA concepts, and LVF sigma usage.
- Mixed-signal/PHY boundary timing (e.g., DDR, PCIe, SerDes).
- Data pipeline skills (dashboards, databases) and/or scaling regressions on cloud/HPC.
We have a flexible work environment to support and help employees thrive in personal and professional capacities. You’ll also be eligible for competitive benefits described as per below: Health & Wellness Our programs emphasize knowledge and prevention, helping you stay proactive and prepared to manage your health at every stage.
- Comprehensive health plan
- Health Spending Account (HSA)
- Wellness Spending Account (WSA)
- Employee Assistance Program (EAP)
Time Off We value the importance of rest and recharge, which is why we offer flexible time off options to support your well-being.
- Paid Vacation
- Paid Holidays
- Parental Leave Top-Up Program
Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.
About Alphawave Semi
We work to create silicon that enables the highest performing, most reliable and lowest power digital communication networks.
Alphawave Semi is a global leader in high-speed connectivity for the world’s technology infrastructure. Faced with the exponential growth of data, Alphawave Semi’s technology services a critical need: Enabling data to travel faster, more reliably and with higher performance at lower power.
We are a vertically integrated semiconductor company, and our IP, custom silicon, and connectivity products are deployed by global tier-one customers in data centers, compute, networking, AI, 5G, autonomous vehicles, and storage. Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, our mission is to accelerate the critical data infrastructure at the heart of our digital world.