Top Benefits
Private medical, life insurance, contributory pension
Equity participation
28 days annual leave + bank holidays, enhanced family leave
About the role
Who you are
- Proficiency in Python
- Solid understanding of low-level computer architecture
- Willingness to learn about FPGA development, quantum computing, and quantum error correction
- Familiarity with quantum computing or quantum error correction
- Understanding of optimisation concepts
- Exposure to networking principles
- Experience with RTL (Register Transfer Level) development for FPGA/ASIC
- Please note, for PhD students, there is the requirement to temporarily step out of your PhD to complete the internship, which may impact your right to work status
- You must be available full-time for 10 to 12 weeks over the summer vacation period, preferably starting on Monday 15th June 2026 until Friday 4th September 2026
- We require a signed agreement from you assigning the ownership of any IP produced during your internship to Riverlane
What the job involves
- Riverlane’s Local Clustering Decoder (LCD) is at the forefront of quantum error correction, capable of decoding surface code quantum memory experiments in under 1 microsecond per round of syndrome extraction - fast enough to keep up with today’s fastest superconducting qubits
- Its architecture already supports a wide variety of logical qubit operations that will be essential for the fault-tolerant quantum computers of the near future
- As an Engineering Intern, you will be responsible for investigating and implementing architectural optimisations that unlock greater flexibility and performance in the LCD decoder. Your work will help ensure this system meets the demands of next-generation quantum hardware, expected to come online within the next five years
- Collaborate with experienced hardware and software engineers to explore and evaluate architectural optimisations
- Enhance the decoder’s architecture to improve both flexibility and processing speed
- Contribute to key design decisions involving space/time trade-offs to balance functionality with performance
The application process
- Please upload a CV and covering letter here. Your CV should include the grades that you have so far received in your degree(s). The covering letter should explain why you are applying for the internship and what skills and experience you can bring to the role
- Our summer internships start on Monday 15th June 2026 until Friday 4th September 2026
- Please submit your application by Sunday 16th November 2025. Interviews will be held in Cambridge (or virtually if required) during late November/early December 2025
Benefits
- A comprehensive benefits package that includes private medical insurance, life insurance and a contributory pension scheme
- Equity so that our team can share in the long-term success of Riverlane
- 28 days annual leave plus bank holidays and enhanced family leave
About Riverlane
Software Development
51-200
Riverlane’s mission is to make quantum computing useful sooner. To achieve this, Riverlane is building the Quantum Error Correction Stack to comprehensively correct the millions of data errors that prevent today’s quantum computers from achieving useful scale.
Top Benefits
Private medical, life insurance, contributory pension
Equity participation
28 days annual leave + bank holidays, enhanced family leave
About the role
Who you are
- Proficiency in Python
- Solid understanding of low-level computer architecture
- Willingness to learn about FPGA development, quantum computing, and quantum error correction
- Familiarity with quantum computing or quantum error correction
- Understanding of optimisation concepts
- Exposure to networking principles
- Experience with RTL (Register Transfer Level) development for FPGA/ASIC
- Please note, for PhD students, there is the requirement to temporarily step out of your PhD to complete the internship, which may impact your right to work status
- You must be available full-time for 10 to 12 weeks over the summer vacation period, preferably starting on Monday 15th June 2026 until Friday 4th September 2026
- We require a signed agreement from you assigning the ownership of any IP produced during your internship to Riverlane
What the job involves
- Riverlane’s Local Clustering Decoder (LCD) is at the forefront of quantum error correction, capable of decoding surface code quantum memory experiments in under 1 microsecond per round of syndrome extraction - fast enough to keep up with today’s fastest superconducting qubits
- Its architecture already supports a wide variety of logical qubit operations that will be essential for the fault-tolerant quantum computers of the near future
- As an Engineering Intern, you will be responsible for investigating and implementing architectural optimisations that unlock greater flexibility and performance in the LCD decoder. Your work will help ensure this system meets the demands of next-generation quantum hardware, expected to come online within the next five years
- Collaborate with experienced hardware and software engineers to explore and evaluate architectural optimisations
- Enhance the decoder’s architecture to improve both flexibility and processing speed
- Contribute to key design decisions involving space/time trade-offs to balance functionality with performance
The application process
- Please upload a CV and covering letter here. Your CV should include the grades that you have so far received in your degree(s). The covering letter should explain why you are applying for the internship and what skills and experience you can bring to the role
- Our summer internships start on Monday 15th June 2026 until Friday 4th September 2026
- Please submit your application by Sunday 16th November 2025. Interviews will be held in Cambridge (or virtually if required) during late November/early December 2025
Benefits
- A comprehensive benefits package that includes private medical insurance, life insurance and a contributory pension scheme
- Equity so that our team can share in the long-term success of Riverlane
- 28 days annual leave plus bank holidays and enhanced family leave
About Riverlane
Software Development
51-200
Riverlane’s mission is to make quantum computing useful sooner. To achieve this, Riverlane is building the Quantum Error Correction Stack to comprehensively correct the millions of data errors that prevent today’s quantum computers from achieving useful scale.