This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior ASIC Design Verification Engineer based in Canada. This role sits at the forefront of advanced semiconductor innovation, focused on enabling next-generation Ethernet-based architectures for autonomous systems, robotics, and software-defined vehicles. You will be responsible for leading and executing full-chip verification efforts for complex SoC designs that power high-reliability, high-performance automotive and intelligent machine applications. The position requires deep technical expertise in verification methodologies, combined with the ability to collaborate closely with architects, designers, and software engineers to ensure robust, scalable, and production-ready silicon. You will contribute across the entire verification lifecycle, from early specification analysis through coverage closure and post-silicon validation support. This is a highly technical, hands-on role in a fast-paced, engineering-driven environment where precision, collaboration, and innovation are essential. You will help shape cutting-edge networking and compute technologies that directly impact the future of autonomous mobility and intelligent systems. The environment is globally distributed, highly collaborative, and built around deep engineering excellence. \n

Accountabilities: Lead and execute end-to-end digital SoC verification activities for advanced automotive communication and networking semiconductor designs. Develop, implement, and maintain verification environments using SystemVerilog, UVM, and supporting languages such as Python, TCL, and C/C++. Work closely with architects, designers, and software engineers to define verification strategy, test plans, and coverage goals from specification through silicon validation. Perform functional verification, debugging, and root cause analysis of simulation failures across complex SoC subsystems. Drive coverage closure, regression strategy, and verification sign-off processes to ensure design completeness and correctness. Contribute to modular, reusable, and scalable testbench architectures and verification infrastructure. Support automation initiatives across test generation, regression execution, and verification tool flows. Collaborate across multidisciplinary and international teams to ensure alignment and high-quality delivery of verification milestones. Requirements: 10+ years of ASIC design verification experience in complex SoC or semiconductor environments. Strong understanding of ASIC verification methodologies, including constrained-random verification and functional coverage. Advanced proficiency in SystemVerilog, UVM, and scripting languages such as Python, TCL, and C/C++. Experience across the full verification lifecycle, including spec analysis, test planning, simulation, coverage closure, and gate-level verification. Strong debugging skills with the ability to isolate and resolve complex design and simulation issues. Experience with networking protocols such as Ethernet, switching, TCP/IP, PCIe, or similar is highly desirable. Exposure to modular testbench design, reusable verification components, and scalable verification frameworks. Familiarity with automation of verification flows, regression systems, or EDA tooling is a strong asset. Strong communication and documentation skills with high attention to detail. Ability to work independently while collaborating effectively across global engineering teams. Benefits: Competitive compensation and pre-IPO stock option opportunities. Comprehensive health benefits including medical, dental, and vision coverage. Flexible working hours with remote-first or hybrid flexibility in Canada. Opportunity to work on cutting-edge semiconductor technologies for autonomous systems and intelligent machines. High-impact role with strong technical ownership and visibility across the engineering organization. Collaborative, world-class engineering team with deep domain expertise. Strong career growth opportunities within a rapidly scaling deep-tech environment. Access to advanced engineering tools, methodologies, and complex system design challenges.

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