Position: Analog Layout Engineer/Lead (RF/Analog IC Design) Location: Onsite- Vancouver, BC Job type: Full-Time/Permanent Hiring

Seeking an experienced Technology Lead – Analog Layout with strong expertise in RF/Analog custom layout, FinFET technologies, and deep sub-micron CMOS design. The role focuses on transistor-level layout development, verification, and optimization of high-performance RF and analog circuit blocks for advanced semiconductor platforms.

Key Responsibilities Design and develop transistor-level layouts for RF/analog blocks including PLL, LNA, Mixer, ADC/DAC, PA, filters, and LDOs. Perform layout verification using DRC, LVS, ERC, extraction, and DFM flows. Optimize layouts for matching, parasitic reduction, shielding, electromigration, and high-frequency routing. Work with Cadence Virtuoso Layout XL and Calibre verification tools. Support FinFET-based advanced node designs (N5/N3/N2 technologies). Collaborate with RF designers and layout engineers to ensure high-quality layout delivery. Must-Have Skills Strong experience in custom RF/Analog layout design. Expertise in FinFET technologies (N5/N3/N2 or advanced nodes). Hands-on experience with Cadence Virtuoso Layout XL. Strong knowledge of Calibre DRC/LVS/ERC verification flows. Understanding of deep sub-micron CMOS layout techniques. Experience with RF shielding, device matching, coupling, RC delay, and electromigration.