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Job Description

Microchip Technology FPGA Business group is seeking a highly skilled and experienced Memory Interconnect System Architect to join our dynamic team. The successful candidate will be responsible for leading cross-functional teams to deliver high-performance IP integrations into our FPGA products, that meet market & customer requirements across a broad range of use cases & application spaces.

This position is in the Silicon Architecture team of Microchip’s FPGA Division. Microchip is a major supplier of low-power and highly-reliable field-programmable gate arrays (FPGAs). Our FPGAs are used in a wide variety of applications, including embedded vision; digital signal processing; machine learning; industrial and medical equipment; and satellites. Microchip is also a pioneer in embedding RISC-V processors in FPGAs.

The successful applicant will work as part a core team to develop future FPGA device products and will collaborate with other engineering disciplines to model, develop, verify, and integrate Interconnect components such as IO, hard Memory IP blocks, hard & soft IP solutions, that interoperate with overall configuration and security features to deliver performant FPGA products.

Key Responsibilities

• Lead cross-functional teams to deliver high-performance IP integrations into Microchip FPGA products
• Work on architecture & implementation for Analog, ASIC & FPGA design development, integration, and deployment for high performance parallel interconnect, such as low voltage / high speed single ended and differential standards supporting protocols such as LP/DDR, LVDS, MIPI data & clocking.
• Understand customer use cases and the role of IP in overall system architecture
• Work cross-functionally with other architects, designers, and back-end implementation teams
• Lead and manage other engineers in the team

Requirements/Qualifications

• Proven experience in ASIC & FPGA IP development, integration, and deployment, including all stages of development from Synthesis, constraint management, place & route, floorplanning, timing closure, CDC/RDC
• Knowledge and experience with system-level performance modeling in TLM/SystemC/Other will be an advantage
• Experience in technical leadership and people management will be an advantage
• Proven ability to work cross-functionally with other architects, designers, and back-end implementation teams
• Knowledge and experience with Synopsys & Cadence ASIC flows
• Scripting for EDA in Perl, Python, Tcl will be an advantage
• Experience in technical leadership and people management will be an advantage
• MSc or higher in EE, CS, CE or other applicable disciplines
• 15+ years of industrial experience

Travel Time

0% - 25%

Pay Range

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position is 107,000 - 226,000.*

• Range is dependent on numerous factors including job location, skills and experience.

Ontario Accommodation

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