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Hybrid · Markham
The engineer will lead PPA improvements for critical graphics blocks and serve as the primary point of contact between Physical Design and RTL teams. They will collaborate with cross-functional teams to optimize design recipes, resolve timing bottlenecks, and influence architectural decisions from concept to tape-out.
On-site · Markham
Define the IOHUB verification strategy and scope while developing comprehensive test plans. Collaborate with design and architecture teams to implement verification components and drive verification closure.
On-site · Markham
Develop and maintain block-level RTL IP and MP subsystems, including feature specifications and micro-architecture design. Coordinate IP integration flows and resolve technical issues with SoC integration and validation teams.
On-site · Ottawa
Develop synthesizable RTL for IP cores targeting advanced technology nodes and collaborate with architecture, verification, and SoC integration teams. Contribute to design specifications and ensure power, performance, and area goals are met through synthesis and timing closure support.
On-site · Ottawa
The Program Manager will lead key engineering initiatives from concept through execution, ensuring alignment across hardware, firmware, and software teams. They are responsible for defining project plans, managing schedules, and mitigating risks to ensure high-quality product delivery.
On-site · Markham
Architect, develop, and maintain robust Windows installers and deployment frameworks for desktop, device, and AI-enabled applications. Collaborate with cross-functional teams to ensure installation reliability, performance, and seamless integration of AI-assisted development tools.
On-site · Markham
The role involves leading the RTL design team to define, develop, and maintain functional specifications for security IP and hardware accelerators. You will collaborate across cross-functional teams to drive design optimization, ensure quality metrics are met, and mentor engineering staff.
On-site · Markham
Develop and maintain block-level RTL IP and microprocessor subsystem specifications, microarchitecture, and RTL implementations. Collaborate with cross-functional teams to debug integration issues and achieve functional, timing, and power closure.
Hybrid · Markham
Develop, test, and implement code for product security within a custom application environment. Collaborate with global operations teams to analyze system performance and improve infrastructure security.
On-site · Markham
The role involves designing, implementing, and verifying embedded firmware for IP sub-systems within pre-silicon and post-silicon environments. You will collaborate with cross-functional teams to drive hardware and firmware co-development while applying AI-driven tools to optimize workflows.
Hybrid
The lead will design and optimize scalable build infrastructure to improve engineering productivity and turnaround times for CPU core development. They will also provide technical leadership in modernizing build systems and partner with cross-functional teams to define long-term automation strategies.
On-site · Markham
The Systems Validation Engineer will execute SOC and system-level validation, triage, and debug for Data Center GPU products across pre-silicon and post-silicon phases. They will collaborate with cross-functional teams to plan validation content, improve automation, and drive technical issues to closure.
Hybrid · Markham
Provide technical leadership for the development of next-generation IOHUB IP, ensuring successful execution from architecture through tape-out and post-silicon validation. Collaborate with cross-functional teams to define requirements, drive design quality, and implement scalable solutions for high-performance computing products.
On-site · Markham
The Systems Design Engineer will own and drive the debugging of hardware and software failures on prototype and production silicon. They will collaborate with design and software teams to isolate root causes and implement effective fixes.
On-site · Markham
The Senior Vendor Technology Program Manager will define and implement vendor qualification processes while acting as the primary liaison between AMD cross-functional teams and external partners. They are responsible for managing technical requirements, assessing vendor performance, and ensuring alignment with the product roadmap for high-performance computing and AI infrastructure.
Hybrid · Markham
Architect, develop, and scale AI fleet management solutions across global regions while driving performance optimization and reliability. Influence the long-term architectural evolution of AI compute solutions and leverage AI to enhance organizational productivity.
Hybrid · Markham
Collaborate with cross-functional teams to design, develop, and maintain ROCprofiler-SDK components for GPU performance profiling. Optimize profiling tools for accuracy and scalability while debugging issues across application, driver, firmware, and hardware layers.
Hybrid · Markham
The role involves managing standard cell library development, including vendor communication, scheduling, and quality assurance. You will also drive the release process and address technical issues related to standard cells for internal customers.
Hybrid · Markham
Develop and maintain full-stack applications, automation services, and AI-powered tools to enhance engineering productivity. Drive DevOps best practices and integrate AI-driven capabilities into semiconductor design and verification workflows.
Hybrid · Markham
The engineer will define circuit architectures for high-bandwidth electrical and optical links and perform link-level simulations. They are also responsible for designing and modeling on-die RF passive components and various circuit blocks like DACs, ADCs, and PLLs.
