We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_
On-site · Markham
Develop and drive the execution of comprehensive software for new technology and product introduction projects. Collaborate with cross-functional teams to validate new features and design future system architectures.
Hybrid · Markham
The role involves owning the end-to-end delivery of infrastructure firmware features, including design, implementation, and validation. You will also lead by influence, mentoring junior engineers and driving technical alignment across cross-functional teams.
On-site · Markham
The Lead SMU Validation Engineer will drive hardware and power-management validation for Data Center GPU products across the entire product lifecycle. They will lead debug triage, develop validation plans, and partner with cross-functional teams to ensure high-quality delivery of AI and HPC products.
Hybrid · Markham
The role involves developing and executing comprehensive software for new technology and product introduction projects. You will collaborate with cross-functional teams to validate features and design future system architectures.
Hybrid · Markham
The role involves owning the end-to-end delivery of infrastructure firmware features, including design, implementation, validation, and release. You will also lead by influence, mentoring junior engineers and driving technical alignment across cross-functional teams.
Hybrid · Markham
The Lead SMU Validation Engineer will drive hardware and power-management validation for Data Center GPU products across pre-silicon, bring-up, and post-silicon phases. They will lead debug triage, root-cause analysis, and collaborate with cross-functional teams to ensure high-quality product delivery.
Hybrid · Ottawa
The SoC DFX Staff Engineer will design and integrate robust Design for Test and Design for Debug solutions for high-performance SoCs. They will collaborate with cross-functional teams to build test plans, execute verification, and resolve design defects throughout the product lifecycle.
Remote · Ontario, Canada
The program manager will lead the deployment and operation of internal Instinct fleet systems by coordinating across engineering and cross-functional teams. They are responsible for defining project plans, managing risks, and providing status updates through performance data and dashboards.
On-site · Markham
Support day-to-day operations using AI tools and maintain operations database systems and automation processes. Collaborate with the Program Management Operations team to research new technologies and execute project initiatives.
On-site · Markham
The role involves supporting day-to-day operations using AI tools and maintaining database systems, reports, and automation processes. The engineer will also research new technologies and collaborate with the Program Management Operations team to execute projects.
On-site · Markham
The role involves supporting daily operations through AI tools, database management, and automation processes. The engineer will also collaborate with departments to plan projects and research new technologies for operational improvement.
On-site · Markham
The role focuses on power-constrained performance modeling and architecture definition for AI/ML/HPC accelerators from pre-silicon to product launch. Responsibilities include developing ML-based modeling solutions and collaborating cross-functionally to optimize power efficiency and PPA targets.
Hybrid · Markham
Collaborate with architects and design teams to verify performance features for complex multi-subsystem IP. Develop test plans, drive regression triage, and analyze performance results to resolve hardware and configuration issues.
Hybrid · Markham
Develop and enhance System Verilog/UVM-based testbenches to verify PCIe features and ensure RTL design robustness. Collaborate with architects, RTL designers, and performance engineers to create comprehensive test plans and improve productivity through automation.
On-site · Markham
The engineer will support power-constrained performance modeling, projections, and target setting for AI/ML/HPC accelerators from concept to product launch. They will also contribute to power management architecture definition and develop ML-based modeling solutions to improve prediction accuracy and scalability.
On-site · Calgary
Design and develop high-performance math libraries and Tensor operations for next-generation GPU architectures. Collaborate with architecture specialists to enhance software capabilities and improve future hardware products.
On-site · Calgary
Design and develop high-performance software technologies and GEMM/Tensor operations for GPU architectures. Collaborate with architecture specialists to enhance existing products and bring new GPU hardware to market.
On-site · Markham
Coordinate and drive the execution of Security IP projects across various SOC programs at AMD. This includes developing project schedules, managing risks, and facilitating alignment between Security IP and SoC teams.
On-site · Markham
Develop and deploy AI-driven automation workflows to improve the efficiency and scalability of complex package, bridge, and interposer designs. Collaborate with EDA vendors and internal teams to optimize auto-routing, placement, and design rule compliance.
On-site · Markham
Develop and deploy AI-driven automation frameworks to improve the efficiency and quality of complex package, bridge, and interposer designs. Collaborate with EDA vendors and internal teams to optimize auto-routing, placement, and design rule compliance.
