ASIC Engineer Intern

Original job posting

The intern will contribute to the development and evolution of automation infrastructure for next-generation ASIC devices. Responsibilities include collaborating on ASIC design, layout, integration, and verification activities while enhancing Python-based workflows.

Job details

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters. The Opportunity: Work term of 4 months extendable to 8, starting in January 2027. Ciena is seeking a student to contribute to the development and evolution of automation infrastructure used for next-generation ASIC devices. The role provides exposure to ASIC design, integration, layout, and verification activities within large-scale DSP ASIC development for optical communications. The position is aligned to a student’s experience, strengths, and technical interests. How you will make an impact: Contribute to the development of automation infrastructure for ASIC devices. Collaborate with developers and team leads to advance ASIC design, layout, integration, and verification activities. Develop design blocks and evaluate designs for correctness and performance. Implement netlists into silicon-realizable layouts and automate placement and extraction workflows. Create constraints, analyze implementation reports, and automate ASIC integration processes. Develop reusable SystemVerilog/UVM verification components. Enhance Python-based reporting, analysis, build, simulation, and debug workflows. The must haves: Programming experience using one or more of Java, Python, TCL, Skill/Ocean, or SystemVerilog. Familiarity with Linux-based development environments. Nice to haves: Previous experience with ASIC or FPGA development programs. Strong analytical and debugging skills. Familiarity with Agile, JIRA, Confluence, and Git. Pay Range: The hourly pay range for this position is $25.50 - $35.00. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

What you’ll do

The intern will contribute to the development and evolution of automation infrastructure for next-generation ASIC devices. Responsibilities include collaborating on ASIC design, layout, integration, and verification activities while enhancing Python-based workflows.

Requirements

Candidates must have programming experience in languages such as Java, Python, TCL, or SystemVerilog and familiarity with Linux environments. Previous experience with ASIC or FPGA development programs is considered a strong asset.

Benefits

• Employee Assistance Program
• Company-paid holidays
• Paid sick leave
• Vacation pay

Listed skills

• Java · Preferred
• Python · Preferred
• Linux · Preferred
• Agile · Preferred
• Jira · Preferred
• Git · Preferred
• Integration · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• Java
• Python
• TCL
• Skill/Ocean
• SystemVerilog
• Linux
• ASIC design
• FPGA development
• Debugging
• Agile
• JIRA
• Confluence
• Git
• Verification
• Layout
• Integration
• Atlassian Confluence
• Workflow Management
• Git (Version Control System)
• Agile Methodology
• Artificial Intelligence
• Automation
• Digital Signal Processing
• Extensible Authentication Protocol
• Field-Programmable Gate Array (FPGA)
• Innovation
• Python (Programming Language)
• Optical Communication
• Simulations
• SystemVerilog (Direct Programming Interface)
• Tcl (Programming Language)
• Application Specific Integrated Circuits

Job areas

• Technology
• Engineering
• Software
• ASIC Engineer
• Hardware Design Engineer
• Electronics Engineers
• Computer Hardware Engineers