Custom IC Layout Engineer

Ottawa, ON
On-site
Posted Oct 8, 2026
1 position

$90,000–$140,000 / year

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Employment type: Full-time
Experience level: Mid-level · 2+ years
Minimum education: College diploma
Apply by: Apr 4, 2027
Posting language: English
Working hours: 40 hours per week
Seniority: Entry level
Application method: Direct apply is available

Job summary

Develop and optimize custom layouts for analog, RF, and mixed-signal integrated circuits, including laser/EAM drivers and TIAs, and support block- and top-level integration. Run physical verification, assist with resolving layout issues, support parasitic extraction and post-layout simulation, and collaborate with circuit designers and senior layout engineers.

Job details

About Inpho Inpho is a fast-growing scale-up, focused on developing cutting-edge optoelectronic solutions for next-generation communications, and photonic systems. Our multidisciplinary team is pushing the boundaries of innovation in integrated photonics and semiconductor packaging. Inpho’s new class of electro-photonic chips is poised to revolutionize and disrupt the optical interconnect market. Utilizing this new class of chips enables existing optical interconnect systems to be built at much lower cost; new architectures to be deployed that provide significantly higher price/performance; and a whole new generation of higher speed interconnect to be built that to date have been impossible. About the Role We are seeking a Custom IC Layout Engineer who will contribute to Inpho’s innovative products, designing and implementing industry leading laser/EAM drivers and TIAs in both SiGe and InP. This includes fully integrated electronic-photonic ICs that are unique in the industry. Key Responsibilities Develop and modify custom IC layouts based on schematics and guidance from senior layout engineers. Perform device placement, routing, floorplanning, and basic layout optimization. Apply fundamental layout techniques including symmetry, matching, shielding, guard rings, and dummy structures. Work closely with circuit designers and senior layout engineers to understand circuit requirements and layout constraints. Run and debug physical verification checks, including DRC, LVS, and ERC, and assist with resolving layout and verification issues. Support parasitic extraction and post-layout simulation activities. Assist with block-level and top-level layout integration. Learn and adopt best practices for layout quality, manufacturability, and reliability. Contribute to improving layout workflows and reusable layout components. Qualifications College diploma or above. Minimum 2 years of hands-on IC layout experience, ideally in analog, RF, or mixed-signal design. Working knowledge of CMOS, BiCMOS, and SiGe process technologies. Proficiency in Cadence Virtuoso or Keysight ADS layout (at least one required; experience in both is a plus). Familiarity with Calibre, Assura, and/or PVS for DRC, LVS, and parasitic extraction. Basic understanding of high-speed layout practices: symmetric/matched routing, guard-ringing, shielding, and controlled-impedance interconnect. Willingness and demonstrated aptitude to be trained on InP HBT and compound-semiconductor layout methodology. Strong communication skills and the ability to work independently and as part of a fast-paced engineering team. Preferred Experience Exposure to ESD structure layout Exposure to RF-specific layout elements (spiral inductors, transmission lines, via stitching, ground stitching) Startup or high-growth environment experience. Why Join Inpho? Be part of a mission-driven startup shaping the future of photonics Competitive salary, full health benefits and equity packages, flexible work environment, and career growth opportunities Come work with a dynamic, high-talent team to build and commercialize the highest-performance photonics chips in the world! Additional Information This posting is for a newly created position. The expected compensation range for this position is CAD$90,000 - $140,000 annually. Actual compensation offered for this position will be determined based on a variety of factors, including the candidate’s skills, level, experience, qualifications, and overall fit for the role. Inpho may use Artificial Intelligence (AI) to support aspects of the recruitment process, including candidate screening and assessment. All final hiring decisions are made by Inpho’s Hiring Team. Inpho is an equal opportunity employer committed to fostering an inclusive, diverse, and respectful workplace. We provide equal employment opportunities without discrimination based on race, colour, religion, sex, gender identity or expression, sexual orientation, national origin, age, disability, veteran status, or any other characteristic protected by applicable law. If you require accommodation during the recruitment process, please contact Inpho Human Resources at hr@inpho.io We thank all candidates for their interest in Inpho. Only those candidates selected for an interview will be contacted.

What you’ll do

Requirements

Requires a college diploma or higher and at least two years of hands-on IC layout experience, ideally in analog, RF, or mixed-signal design. Candidates should know CMOS, BiCMOS, and SiGe technologies and have experience with Cadence Virtuoso or Keysight ADS; familiarity with physical verification tools and high-speed layout practices is also expected.