Memory Layout Design Engineer
The role involves designing and developing high-performance custom memory layouts and leaf cell libraries from scratch. It also requires optimizing layouts for power, performance, and area while performing rigorous physical verification.
- On-site
- Vancouver, BC
- Posted Jul 23, 2026
- Apply by Aug 22, 2026
- 1 position
Job summary
Position: Memory Layout Design Engineer Location: Vancouver, BC (On-site) Employment Type: Full-Time Total Experience: 5 + years Job Summary: We are looking for an experienced Technology Lead – Memory Layout to design and develop high-performance custom memory layouts for advanced semiconductor technologies. The ideal candidate should have strong expertise in memory layout design, physical verification, FinFET technologies, and memory architectures. Key Responsibilities: · Design and develop custom memory layouts and memory leaf cell libraries from scratch. · Optimize layouts for performance, power, and area (PPA). · Work on various memory architectures and top-level layout integration. · Perform physical verification (DRC, LVS, ERC) and resolve layout issues. · Develop layouts using Cadence Virtuoso and verify designs with Calibre. · Collaborate with cross-functional teams to ensure high-quality and timely project delivery. Required Qualifications: · Bachelor's degree in engineering or equivalent experience. · 5+ years of experience in compiler/custom memory layout design. · Hands-on experience with memory leaf cell layout development. · Strong knowledge of memory architectures and FinFET technology (3nm/5nm). · Experience with DRC, LVS, ERC, boundary conditions, Cadence Virtuoso, and Calibre. · Strong problem-solving, communication, and teamwork skills. · Must be willing to work on-site in Vancouver, BC or relocate.
What you’ll do
The role involves designing and developing high-performance custom memory layouts and leaf cell libraries from scratch. It also requires optimizing layouts for power, performance, and area while performing rigorous physical verification.
Requirements
Candidates must have a bachelor's degree and over 5 years of experience in custom memory layout design, specifically with FinFET technologies (3nm/5nm). Proficiency in Cadence Virtuoso and Calibre for DRC, LVS, and ERC is essential.
Other relevant skills
Identified from the job description. Confirm important requirements above.
- Memory Layout Design
- Physical Verification
- FinFET Technology
- Memory Architectures
- Cadence Virtuoso
- Calibre
- DRC
- LVS
- ERC
- PPA Optimization
- Custom Memory Layouts
- Leaf Cell Library Development
Job areas
- Engineering
- Manufacturing
- Technology
- Science & Research
Additional details
- Minimum education
- Bachelor’s degree
- Minimum experience
- 5+ years
- Apply by
- Aug 22, 2026
- Posting language
- English
- Working hours
- 40 hours per week
- Seniority
- Mid-Senior level
- Application method
- Direct apply is available