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Design Verification Engineer

  • Canada
  • Remote
  • Posted Oct 20, 2026
  • 1 position

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Employment type
Contract
Experience level
Senior · 5+ years
Posting language
English
Working hours
40 hours per week
Seniority
Mid-Senior level
Application method
Direct apply is available

Job summary

Own verification for 4–5 ASIC design blocks, including developing and executing sequences and tests, debugging, and driving coverage collection and closure. Independently manage end-to-end verification deliverables for assigned blocks and collaborate with the customer in the EST time zone.

Job details

Job Title/Role: DV Engineer – ASIC Verification Mode: Remote (Canada) Type: Contract (Long Term) Location: Canada ASIC Programs (Switch/NIC) DV • Lead or contribute to verification of 4–5 ASIC design blocks. • Develop UVM-based verification environments, sequences, tests, debug, and coverage closure. • Strong experience in SystemVerilog/UVM. • Ability to independently own verification deliverables. • Support customer collaboration in EST timezone. Required Skills • Strong SystemVerilog/UVM verification experience • Knowledge and/or hands-on experience with: o Ethernet • Ability to own design blocks independently and drive verification closure Responsibilities The DV team is expected to: • Own verification of 4–5 design blocks per ASIC • Develop and execute sequences • Perform test development and debug • Drive coverage collection and closure • Own end-to-end verification execution for assigned blocks • The customer will own the testbench infrastructure. • Knowledge of PCIe, UCIe 2.0, and Ethernet protocols is a plus. If you're interested, please share your updated resume and a good time to connect.

What you’ll do

Own verification for 4–5 ASIC design blocks, including developing and executing sequences and tests, debugging, and driving coverage collection and closure. Independently manage end-to-end verification deliverables for assigned blocks and collaborate with the customer in the EST time zone.

Requirements

Strong SystemVerilog and UVM verification experience is required, along with the ability to independently own design blocks and drive verification to closure. Ethernet knowledge or hands-on experience is sought; PCIe and UCIe 2.0 knowledge are additional advantages.

Listed skills

  • Customer · Preferred
  • Time · Preferred
  • Collaboration · Preferred
  • Development · Preferred
  • Execution · Preferred
  • Organization · Preferred
  • Attention to detail · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

  • SystemVerilog
  • UVM
  • ASIC Verification
  • Verification Environment Development
  • Sequence Development
  • Test Development
  • Debugging
  • Coverage Collection
  • Coverage Closure
  • Ethernet
  • PCIe
  • UCIe 2.0
  • Design Block Ownership
  • Customer Collaboration

Job areas

  • Engineering
  • Technology
  • Software

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