Analog Design Engineer

Job summary

The engineer will design and execute analog/mixed-signal building blocks for high-performance wireline transceivers. Responsibilities include porting schematics to new technology nodes, performing simulations, and guiding layout designers.

Job details

Pay Rate: $55.00/hr - $58.00/hr Duration: 12 months Contract - chances of extension Location: Remote (anywhere from Canada) Job Description: Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process. We are currently seeking an analog/mixed-signal designer to work on analog and mixed-signal building blocks in wireline transceivers. The candidate will be responsible for: Own and execute analog/mixed-signal design of blocks, such as low-dropout regulators (LDOs), bandgap circuits, analog bias circuits, amplifiers, clocking circuits, ADCs and DACs. Port schematics into new technology nodes (Ex. from N3 to N2) Implement and optimize circuits for meeting the defined block specifications and functionality requirements Guide the layout designer(s) to implement the layout of the circuit blocks, and manage the quality of layout and floorplan of the circuit blocks Perform pre-layout (schematic) simulations and post-layout simulations Deliver the design reviews based on SerDes team’s design methodology and design review requirements Experience and Education: 3-7 years of relevant work experience; Experience with Schematic Design and Circuit Simulation in Cadence Virtuoso Experience in circuit reliability and EMIR verification of analog/mixed signal blocks Experience in advanced CMOS process technology nodes (N7,N6, N5, N3, N2…etc) is preferred

What you’ll do

The engineer will design and execute analog/mixed-signal building blocks for high-performance wireline transceivers. Responsibilities include porting schematics to new technology nodes, performing simulations, and guiding layout designers.

Requirements

Requires 3-7 years of experience with Cadence Virtuoso and circuit simulation in advanced CMOS process nodes. Proficiency in circuit reliability and EMIR verification is essential.

Listed skills

• Organization · Preferred
• Reliability · Preferred
• Attention to detail · Preferred
• Process · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• Analog Design
• Mixed-Signal Design
• Cadence Virtuoso
• Circuit Simulation
• CMOS Process Technology
• LDOs
• Bandgap Circuits
• Analog Bias Circuits
• Amplifiers
• Clocking Circuits
• ADCs
• DACs
• EMIR Verification
• Circuit Reliability
• Layout Guidance
• SerDes

Job areas

• Engineering
• Technology
• Manufacturing
• Science & Research