Sr. Design for Test (DFT) Engineer

Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter! If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders. Lightmatter is (re)inventing the future of computing with light! We are hiring a Sr DFT Engineer to help us build high-performance ASICs for the next generation of AI acceleration systems. In this role, you will be responsible for physical design in leading-edge CMOS technology. This includes synthesis through place and route, timing closure, and tape-out signoff. Responsibilities Perform Design For Test (DFT) insertion on ASIC designs, including internal scan, boundary scan, and memory BIST Perform automatic and targeted test pattern generation Interface with Physical Design and Front End (RTL) Design Perform post-silicon DFT bring-up and test program debug Interface with ATE engineers for test program bring-up and debug Scripting and automation of DFT and ATPG flow Be hands-on from the "nitty gritty" details to high level planning. Requirements Bachelor's degree in Electrical Engineering (or other related fields) Minimum of 13 years of industry experience working as a Design For Test Engineer on ASIC designs Must have completed at least 2 tapeouts Minimum of 2 years of experience with standard DFT CAD tools and flows Hands-on experience in Python, TCL or other scripting environments DFT/post-silicon/ATPG with experience in both ASIC and semi-custom COT flow Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields Ability to react to change and thrive in a fast paced environment Preferred Qualifications Masters degree in Electrical Engineering (or related fields) with 10+ years of DFT experience Experience working on ASIC designs with multiple production-quality ASIC tapeouts Experience interfacing with ATE engineers Experience with ATE test program development Experience with fault modeling Understanding of Timing, Physical Design, and Power impact of DFT structures Proven Knowledge of Basic SoC Architecture and HDL languages like SystemVerilog and chipware components to work hand in hand with RTL designers We offer competitive compensation. The base salary range for this role determined based on location, experience, educational background, and market data. Salary Range: total compensation goes beyond base salary, it also includes a new hire equity grant, annual performance-based equity, and other rewards that recognize your impact and contribution.: $123,000 CAD - $150,000 CAD Benefits Comprehensive Health Care Plan (Medical, Dental & Vision) Retirement Savings Matching Program Life Insurance (Basic, Voluntary & AD&D) Generous Time Off (Vacation, Sick & Public Holidays) Paid Family Leave Short Term & Long Term Disability Training & Development Commuter Benefits Flexible, hybrid workplace model Equity grants (applicable to full-time employees) Benefits eligibility may vary depending on your employment status and location. Lightmatter recruits, employs, trains, compensates, and promotes regardless of race, religion, color, national origin, sex, disability, age, veteran status, and other protected status as required by applicable law. Export Control Candidates should have capacity to comply with the federally mandated requirements of U.S. export control laws.

The role involves performing DFT insertion, including internal scan and memory BIST, on high-performance ASICs. Responsibilities also include post-silicon bring-up, test program debug with ATE engineers, and automating DFT flows.

Candidates must have a Bachelor's degree in Electrical Engineering and at least 13 years of industry experience with a minimum of 2 tapeouts. Proficiency in Python, TCL, and standard DFT CAD tools is required.

• Comprehensive Health Care Plan (Medical, Dental & Vision) • Retirement Savings Matching Program • Life Insurance (Basic, Voluntary & AD&D) • Generous Time Off (Vacation, Sick & Public Holidays) • Paid Family Leave • Short Term & Long Term Disability • Training & Development • Commuter Benefits • Flexible, hybrid workplace model • Equity grants

Identified from the job description. Confirm important requirements above.

• Design For Test (DFT)
• ASIC Design
• Scan Insertion
• Boundary Scan
• Memory BIST
• ATPG
• Post-silicon Bring-up
• Python
• TCL
• SystemVerilog
• Physical Design
• Timing Closure
• Fault Modeling
• SoC Architecture
• HDL
• Tape-out Signoff

• Engineering
• Technology
• Manufacturing
• Software
• Science & Research

Minimum education

Bachelor’s degree

Minimum experience

10+ years

Apply by

Aug 28, 2026

Posting language

English

Working hours

40 hours per week

Seniority

Mid-Senior level

Application method

Direct apply is available