Principal Mixed-Signal Design Engineer

The Opportunity Movellus is pioneering on-chip power management for AI-scale silicon, with IP deployed across millions of units in complex SoC architectures. Our technologies deliver real-time PDN telemetry, Ldi/dt detection, mitigation, DFS, and DVFS. We tackle multi-dimensional engineering challenges at the nexus of digital, analog, signal processing, and control systems. At Movellus, we promise fun, not easy — offering an environment for engineers passionate about leading power efficiency in the AI era. We're looking for a Principal Mixed Signal Design Engineer with depth and breadth of experience to join our team. Key Responsibilities: Circuit Design & Architecture Architect and design high-speed analog and mixed-signal circuits (PLLs, LDOs, references, TDCs, Oscillators, ADCs/DACs) in advanced FinFET nodes. Develop robust behavioral models (SystemVerilog/Verilog-A) and integrate complex mixed-signal IP into SoC environments. Drive end-to-end circuit execution from specification through schematic capture, layout supervision, and verification across PVT corners. Architect chip-level ESD protection networks, clamp structures, and I/O cells ensuring latch-up immunity and long-term reliability. Silicon Execution & Validation Lead post-silicon bring-up, characterization, and root-cause debug in collaboration with validation and product engineering teams. Create and execute comprehensive silicon test plans to correlate physical performance against pre-silicon models. Deliver production-ready mixed-signal IP to internal and external customer platforms. Technical Leadership & Methodology Establish analog design methodologies, design review standards, and tape-out best practices across the engineering organization. Partner cross-functionally with digital design, physical layout, systems, and architecture teams to ensure optimal full-chip integration. Mentor and guide junior and mid-level engineers to scale the team's technical capabilities. Required Qualifications: Education: MS or PhD in Electrical Engineering or a related technical field. Experience: 8+ years of hands-on experience in analog/mixed-signal IC design. Proven history of delivering mixed-signal circuits in advanced CMOS/FinFET nodes. Technical Depth: Deep knowledge of high-speed circuit architectures, signal integrity, and physical-layer design principles. Tool Mastery: Advanced proficiency with industry-standard EDA tools (Cadence/Synopsys) for simulation, layout supervision, and parasitic extraction. Preferred Qualifications Multiple successful tape-outs carried through silicon characterization to high-volume production. Hands-on expertise with post-silicon laboratory debug, ATE test plan development, and DFT techniques. Experience establishing design guidelines and leading multi-disciplinary design reviews. What We Offer A dedicated ambitious team with a vast range of talent across software and hardware. Become part of a growing startup in the chip-making hardware industry. Offices in Markham – Canada, Ann Arbor – Michigan, and San Jose – California. Hybrid working model for all offices. Competitive total compensation package. All regular employees are eligible for company stock in the form of stock options. Comprehensive medical, dental, and vision coverage. Retirement savings through a defined contribution pension or savings plan. Flexible PTO/Paid Time Off policy in addition to statutory holidays.

Architect and design high-speed analog and mixed-signal circuits in advanced FinFET nodes, managing the process from specification to silicon validation. Lead technical methodologies and mentor junior engineers to ensure optimal full-chip integration and reliability.

Requires an MS or PhD in Electrical Engineering with over 8 years of experience in analog/mixed-signal IC design. Must demonstrate proficiency with industry-standard EDA tools and a proven track record of delivering circuits in advanced CMOS/FinFET nodes.

• Stock Options • Medical Insurance • Dental Insurance • Vision Insurance • Retirement Savings Plan • Flexible PTO

Identified from the job description. Confirm important requirements above.

• Mixed-Signal Design
• Analog Circuit Design
• FinFET
• SystemVerilog
• Verilog-A
• PLLs
• LDOs
• ADCs/DACs
• ESD Protection
• Post-Silicon Validation
• Cadence
• Synopsys
• Parasitic Extraction
• Signal Integrity
• Physical-Layer Design
• Technical Leadership

• Engineering
• Technology
• Manufacturing
• Science & Research
• Software

Minimum education

Master’s degree

Minimum experience

10+ years

Apply by

Sep 19, 2026

Posting language

English

Working hours

40 hours per week

Seniority

Mid-Senior level

Application method

Direct apply is available