Senior Digital/FPGA Engineer

We are looking for an engineer to help us build Software Defined Radios (SDRs) for mission critical infrastructure. Our products use FPGAs to provide a high performance interface between data provided over a high speed bus (10/40/100G Ethernet), our internal IP, and high speed converter (DACs/ADCs) devices. Your primary responsibilities require you to design, simulate, implement, and validate, FPGA based architectures that interface with high speed IOs (ADC, DAC, clock) to effectively process that data (filtering, decimating, interpolating), and pass that data over a high speed busses (JESD204B/C, 10/40/100G Ethernet). This position also requires engineers to effectively document and communicate design changes, updates, challenges, to other engineers and a broader team. Mandatory Qualifications Experience in all of the following areas: Experience with Verilog (preferred) or VHDL High speed (>150MHz) digital designs. Digital Test bench creation, simulation, and maintenance Experience with Linux based distributions Working knowledge of C or C++ Minimum Experience Experience directly implementing and debugging in at least three of the following areas: High speed DSP (ex; Filters, Decimators, Interpolators, etc.) design (>150MHz) High speed IO interfaces (ex; 10G/40G/100G Ethernet, PCIe, USB3, etc.) designs (>300MHz) High speed (>325MSPS) Digital and Analog Converter Interfaces (JESD204B/C, LVDS, etc.) Low latency digital modem design (QPSK/QAM/PAM, etc) DDR3/4 Memory Controllers (>1800MT/s) Complex test bench creation using iverilog or verilator Timing closure for large (>90% utilization), complex (>5 clock domains), designs FPGA integration with SoC devices, external chipsets, processors, and/or microcontrollers Optional Qualifications The following skills are desired but not necessarily required for the position: Intel/Altera EDA tooling (Quartus, etc). FPGA integration with SDR systems Ethernet protocol implementations (ie; VITA-49 over UDP) Working in a Linux computing environment. Using version control systems (ie; git) Previous design or manufacturing experience Previous work with Schematic Capture and PCB Layout Linux Kernel driver or API Development Understanding of wireless radio and DSP chains Mixed signal board layout and schematic capture Open source radio projects (ie; OpenBTS, UHD, Yocto)

The engineer will design, simulate, implement, and validate FPGA-based architectures that interface with high-speed I/Os to process data effectively. They will also document and communicate design changes and challenges to the team.

Candidates must have experience with Verilog or VHDL, high-speed digital designs, and Linux-based distributions. They should also have a minimum of three areas of implementation experience in high-speed DSP, IO interfaces, and digital converter interfaces.

Identified from the job description. Confirm important requirements above.

• Verilog
• VHDL
• High Speed Digital Design
• Digital Test Bench Creation
• Linux
• C
• C++
• DSP Design
• High Speed IO Interfaces
• Digital Converter Interfaces
• Low Latency Digital Modem Design
• Memory Controllers
• Test Bench Creation
• Timing Closure
• FPGA Integration
• Ethernet Protocol Implementations

• Technology
• Engineering
• Manufacturing
• Data & Analytics
• Software

Minimum experience

5+ years

Apply by

Dec 7, 2026

Posting language

English

Working hours

40 hours per week

Seniority

Mid-Senior level

Application method

Direct apply is available