Qualcomm is a global leader in wireless technology, delivering innovative solutions for intelligent computing across mobile devices, IoT, automotive, and telecommunications sectors.
San Diego, CA
Inspired by 250 years of American ingenuity, we build technologies that expand what’s possible. From wireless to AI at scale and 6G, our innovations power progress worldwide.
On-site · Ottawa
You will define, model, design, and verify high-performance IP blocks for ASIC and FPGA projects. Additionally, you will lead project execution, develop test plans, and mentor junior engineers.
On-site · Ottawa
The Senior Staff Engineer will lead the verification of high-performance IP blocks and subsystems for next-generation interconnect technologies like PCIe Gen7 and CXL 4.0. They will architect scalable verification environments, drive verification closure, and mentor engineering teams to ensure high-quality product execution.
On-site · Markham
You will collaborate with CPU and SOC architects to develop detailed verification plans and testbenches for micro-architectural validation. Additionally, you will execute these plans, manage regressions, and debug test failures to ensure the design meets launch-ready standards.
On-site · Markham
The role involves maintaining local server racks and on-site devices while building robust, reliable infrastructure for machine learning development. You will manage GitHub runner fleets, optimize CI/CD pipelines, and innovate on workflow orchestration to improve team productivity.
On-site · Vancouver
The role involves managing the complete verification lifecycle for digital power IPs, from system-level concept to tape-out and post-silicon support. Responsibilities include developing testbenches using SystemVerilog-UVM, creating coverage and assertion models, and implementing power-aware UPF verification flows.
On-site · Markham
The engineer will own and deliver key aspects of the AI software stack, including developing optimization algorithms and framework enhancements for neural networks. They will also collaborate with cross-functional teams to profile, debug, and enable state-of-the-art AI models on Qualcomm hardware.
On-site · Vancouver
The role involves comprehensive pre-silicon test planning for digital power IPs and developing testbenches using SystemVerilog-UVM. Additionally, the engineer will deploy power-aware UPF verification flows and create automation to improve overall verification efficiency.
On-site · Markham
The candidate will develop and execute comprehensive verification strategies for complex memory subsystem components including memory controllers and PHY-related logic. Responsibilities include building UVM-based testbenches, creating test plans, and driving functional and code coverage closure.
On-site · Markham
The role involves managing the complete verification lifecycle for digital power IPs, from system-level concept to tape-out and post-silicon support. Responsibilities include developing testbenches using SystemVerilog-UVM, creating coverage and assertion models, and implementing power-aware UPF verification flows.
On-site · Vancouver
Lead and execute the RTL-to-Physical Design frontend flow for complex Camera ISP designs to achieve aggressive PPA targets. Collaborate with cross-functional teams including DFT and Physical Design to drive designs to successful silicon tapeout.
On-site · Vancouver
The role involves managing the complete verification lifecycle for digital power IPs, including test planning and testbench development. Responsibilities also include deploying power-aware UPF verification flows and developing automation to enhance verification efficiency.
On-site · Toronto
The intern will perform validation and verification of hardware IP across various constraints and streamline test infrastructure for subblocks. They will also tune firmware in C/C++/Python environments and design tests for next-generation hardware.
On-site · Ottawa
The intern will contribute to the design and verification of ASIC IP blocks and sub-systems within a team of experienced engineers. Responsibilities include developing verification environments, writing testcases, and tracking bug reports from inception to closure.
On-site · Markham
Develop multimedia and compute subsystem integration verification strategies and test plans while creating environments using UVM/System Verilog. Resolve architecture and design problems while driving productivity improvements and adopting new verification methodologies.
On-site · Toronto
The Physical Design Engineer will drive the backend implementation process, including floor-planning, power planning, and clock tree synthesis. They will also perform PPA optimization, timing closure, and physical verification to ensure high-quality, low-power ASIC designs.
On-site · Markham
The engineer will architect, design, and optimize GPU cores while collaborating with cross-functional teams to meet performance and power goals. They will also assist in developing driver and compiler software and perform functional model simulations to verify graphics correctness.
On-site · Markham
Contribute to core verification during pre and post-silicon phases of next-generation ASICs through simulation and test plan execution. Lead complex debug activities and provide technical supervision to other engineers while collaborating with design teams on verification methodology.
On-site · Vancouver
The candidate will collaborate with architects to design hardware for multimedia and camera image signal processing algorithms. They will also own core-level IP RTL design, perform synthesis, and conduct design rule and low-power checks.
On-site · Markham
The role involves developing high-performance software for AI engines and optimizing neural network runtime performance on Qualcomm hardware. You will collaborate with cross-functional teams to deliver AI stack enhancements and support customer use cases.
On-site · Toronto
The engineer will design, analyze, and optimize high-performance interconnects while overseeing behavioral modeling and mixed-signal system verification. They will also collaborate with cross-functional teams to implement calibration algorithms and maintain power models for high-speed SerDes designs.
