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Qualcomm

Verified Job Source

Qualcomm is a global leader in wireless technology, delivering innovative solutions for intelligent computing across mobile devices, IoT, automotive, and telecommunications sectors.

San Diego, CA

Semiconductor Manufacturing
5,001+ people

About

Inspired by 250 years of American ingenuity, we build technologies that expand what’s possible. From wireless to AI at scale and 6G, our innovations power progress worldwide.

Open positions

Senior ASIC Verification Engineer, Low Power AI Subsystems

On-site · Markham

Contribute to core verification during pre and post-silicon phases of next-generation ASICs through simulation and test plan development. Lead complex debug activities and provide technical supervision to other engineers while collaborating with design teams on verification methodology.

FY27 Intern - Silicon Validation Internship - Canada (16 months)

On-site · Toronto

The intern will contribute to the validation of High-Speed SerDes and Die-to-Die IP prototypes by characterizing analog blocks and ensuring compliance with industry standards. Responsibilities also include developing test methodologies, automating test equipment, and generating validation reports.

FY27 Intern - Analog Design Internship - Canada (12 or 16 months)

On-site · Toronto

The intern will assist the analog design team in ensuring circuit performance meets specifications through modeling, simulation, and peer review. They will also collaborate across functional teams including digital, firmware, and system engineering to support design strategies.

System AI Engineer, Display (New Grad Level and up)

On-site · Markham

You will identify and isolate complex display issues at the silicon level using industry-standard hardware and software debugging tools. Additionally, you will collaborate with cross-functional teams to resolve system-level malfunctions and document debugging procedures for internal and customer use.

Audio/Edge AI Silicon Validation and Firmware Engineer

On-site · Markham

The engineer will perform ASIC silicon bring-up and validation for audio IP cores, DSPs, and AI accelerators. They will also develop functional test plans and collaborate with cross-functional teams to debug and resolve hardware and software issues.

Cross-Functional Engineer, Principal

On-site · Vancouver

The role involves designing and verifying analog/mixed-signal blocks, including SerDes architecture and calibration algorithms. You will collaborate with cross-functional teams to support silicon bring-up, power modeling, and system-level verification.

SOC Design Engineer

On-site · Vancouver

The engineer will define, design, and verify complex ASIC subsystems while collaborating with multi-site teams across the US and India. Responsibilities include developing micro-architecture, implementing RTL, and ensuring design convergence through synthesis and physical design interactions.

Display Senior Software Engineer

On-site · Markham

Design, code, test, and integrate display drivers and embedded software for next-generation consumer devices. Collaborate with global hardware and software teams to troubleshoot complex technical issues and optimize system performance.

Senior ASIC Design Engineer, Low Power AI

On-site · Markham

Develop micro-architecture and module specifications for digital audio and AI IP blocks while integrating them into SoC designs. Collaborate with verification and implementation teams to ensure performance, power, and area objectives are met through rigorous testing and synthesis analysis.

Design Verification Engineer, Senior Staff

On-site · Toronto

Lead verification architecture and execution for DSP products, high-speed SerDes integration, and full-chip SoC verification. Drive verification closure from test planning and UVM environment development through production-oriented ATE vector signoff.

Analog Engineer, Principal

On-site · Toronto

Oversees the definition, design, verification, and documentation of CMOS mixed-signal blocks such as data converters, PLLs, and SERDES. Collaborates with teams to optimize circuit performance, power, and area while managing physical layout and silicon evaluation.