Wafer Product Engineer

Ottawa, ON
On-site
Posted Oct 15, 2026
1 position

$140,000–$160,000 / year

Opens an external site

Employment type: Full-time
Experience level: Senior · 5+ years
Minimum education: Bachelor’s degree
Posting language: English
Working hours: 40 hours per week

Job summary

The Wafer Product Engineer will lead characterization, yield analysis, and manufacturing readiness for semiconductor products from NPI through high-volume production. They will serve as the technical bridge between design, test, and manufacturing teams to ensure products meet quality, reliability, and cost targets.

Job details

Job Title: Wafer Product Engineer Location: Ottawa, ON About Ranovus Ranovus is a semiconductor company with global operations helping power the data behind next generation AI and data center networks. We design and build advanced hardware that moves massive amounts of information quickly and efficiently between computer systems in data centers around the world. Our technology improves performance while reducing energy use and environmental impact, supporting the rapid growth of AI and cloud services. At Ranovus, you’ll join a collaborative, inclusive team that values learning, flexibility, and meaningful work with global impact. Position Summary We are seeking an experienced Wafer Product Engineer to lead characterization, yield analysis, statistical validation, and manufacture readiness for semiconductor products from NPI through high-volume production. As the technical bridge between Design Engineering, Test Engineering, Fabs, OSATs, and Operations, you will define characterization plans, corner-lot strategies, SPC methodologies, and release criteria, using DOE, GRR, Cp/Cpk, correlation analysis, and yield modeling to ensure products are manufacturable, testable, and meet quality, reliability, and cost targets. Key Responsibilities Characterization & Validation: Develop characterization plans and define corner-lot requirements across process, voltage, temperature, and manufacturing lots. Analyze electrical, optical, and functional distributions, set production test limits and guardbands, and drive qualification readiness. Statistical Analysis & Process Capability: Analyze product and manufacturing data; monitor and improve Cp/Cpk, yield, parametric distributions, and process stability. Identify sources of variation, drive corrective actions, and issue reports and recommendations supporting production releases. Design of Experiments (DOE): Plan, execute, and analyze DOEs covering process variables, test conditions, environmental factors, and manufacturing variation to optimize performance and margins; present recommendations to cross-functional teams. MSA & GRR: Lead GRR studies, evaluate measurement capability and repeatability, and improve test robustness and accuracy. Ensure test systems meet statistical requirements and support correlation across engineering systems, ATE, probe, and OSAT test environments. Yield & Quality: Analyze wafer sort and final test yield, lead root cause investigations of yield detractors, assess potential test escapes, and recommend screening improvements. Partner with Design and Test to improve quality and test coverage and drive continuous improvement through defect trend reporting and metrics reviews. Fab & OSAT Interface: Serve as primary technical interface for product-related manufacturing issues. Work with foundries on process performance, excursions, capability trends, and yield programs, and with OSATs on production performance, yield loss, test program implementation, and efficiency. Test Program Quality & Release: Partner with ATE Test Engineers on test effectiveness, guardbands, correlation, characterization coverage, and robustness. Review and approve production test limits, balancing quality, yield, customer requirements, and cost. NPI: Collaborate with Design from concept through volume release while driving DFx. Define manufacturing readiness and release-to-production criteria, participate in design, characterization, and production readiness reviews, complete gate review actions on schedule, and drive successful ramps. Required Qualifications Bachelor's or master’s degree in electrical or computer engineering, Physics, Semiconductor Engineering, Applied Statistics, or a related technical discipline. 5+ years of semiconductor Product Engineering experience, including NPI and production ramp support. Strong understanding of wafer fabrication, assembly, and test processes, with direct experience working with foundries and OSAT partners. Experience leading characterization and yield improvement programs. Technical expertise in characterization methodologies, yield analysis and improvement, Cp/Cpk, SPC, DOE, GRR/MSA, correlation studies, root cause analysis, semiconductor manufacturing processes, wafer sort and final test operations, and product qualification. Preferred Qualifications Experience with advanced semiconductor technologies, such as photonic integrated circuits (PICs), silicon photonics, high-speed SerDes, analog, mixed-signal, or optical products. Knowledge of Advantest V93000 (93K) production test environments. Familiarity with JMP, Minitab, MATLAB, Python, and SQL. Understanding of automotive or telecom quality methodologies. Key Competencies Strong statistical and analytical thinking; data-driven decision making; excellent problem solving; cross-functional leadership and the ability to influence technical direction across organizations; effective communication with internal teams and external partners; and strong project management and prioritization skills. Success Metrics Product yield and Cp/Cpk against targets; characterization quality and completeness; DOE effectiveness; GRR and measurement capability improvements; reduced manufacturing excursions; production ramp success and time-to-production readiness; product quality and customer returns; and yield and cost improvements. Ranovus is an equal opportunity employer and welcomes applicants from all backgrounds and lived experiences, including those from equity deserving and underrepresented communities. We are committed to an accessible recruitment process in accordance with the Accessibility for Ontarians with Disabilities Act. We are committed to delivering a respectful and transparent candidate experience, with clear and timely communication at every stage of the process. Ranovus Inc. is committed to leveraging new technologies and working efficiently. As a result, artificial intelligence systems may be used to support elements of our hiring process. These tools are designed to enhance consistency and efficiency, not replace human judgment. All hiring decisions are made by people, guided by care, context, and fairness. Thank you for your interest in joining Ranovus. We look forward to connecting with you.

What you’ll do

Requirements

Candidates must possess a bachelor's or master's degree in a relevant technical discipline and at least 5 years of semiconductor product engineering experience. Strong expertise in wafer fabrication, statistical analysis methodologies, and direct experience with foundries and OSAT partners is required.