PRINCIPAL AMS LAYOUT ENGINEER

You are an experienced engineering leader with deep expertise in high‑speed analog and mixed‑signal layout. Your background in multi‑Gbps NRZ and PAM‑based SerDes, spanning advanced CMOS, FinFET, and GAA nodes, sets you apart. You excel in environments that value innovation, precision, and collaboration, and you are driven by the challenge of building repeatable, scalable methodologies that empower global engineering teams. You translate complex technical challenges into actionable workflows, communicate clearly across interdisciplinary teams, and align stakeholders around shared goals. Mentoring and knowledge sharing come naturally to you. You thrive in fast‑moving environments, balancing multiple priorities while inspiring excellence in those around you. If you are ready to make a meaningful impact at a global leader in semiconductor technology, Synopsys is your next destination. For additional details and the most recent updates, hit “Apply for job”

Lead high-speed analog and mixed-signal layout engineering for multi-Gbps SerDes. Develop repeatable, scalable methodologies and mentor global engineering teams to ensure technical excellence.

Requires deep expertise in advanced CMOS, FinFET, and GAA nodes with a focus on NRZ and PAM-based SerDes. Candidates must possess strong leadership skills and the ability to translate complex technical challenges into actionable workflows.

Identified from the job description. Confirm important requirements above.

• Analog Layout
• Mixed-Signal Layout
• SerDes
• CMOS
• FinFET
• GAA Nodes
• High-Speed Design
• NRZ
• PAM
• Engineering Leadership
• Workflow Optimization
• Mentoring
• Technical Communication
• Scalable Methodologies

• Engineering
• Technology
• Manufacturing
• Management & Leadership

Minimum experience

10+ years

Apply by

Sep 6, 2026

Posting language

English

Working hours

40 hours per week

Seniority

Mid-Senior level