Design Verification Engineer
The engineer will lead the verification of 4–5 ASIC design blocks by developing UVM-based environments, sequences, and tests. They are responsible for driving coverage collection, performing debug, and ensuring end-to-end verification execution for assigned blocks.
- Remote
- Canada
- Posted Jul 23, 2026
- 1 position
Job summary
Role: Design Verification Engineer Location: Canada, Remote Contract Skill: design verification engineers with UVM, PCIe, UCIe, ethernet verification experienc e ASIC Programs (Switch/NIC) DV• Lead or contribute to verification of 4–5 ASIC design block s.• Develop UVM-based verification environments, sequences, tests, debug, and coverage closur e.• Strong experience in SystemVerilog/UV M.• Experience with PCIe, UCIe 2.0, and Ethernet protocol s.• Ability to independently own verification deliverable s.• Support customer collaboration in EST timezon e. Required Ski lls• Strong SystemVerilog/UVM verification experie nce• Knowledge and/or hands-on experience wi th:o UCIe 2.0o P CIeo Ether net• Ability to own design blocks independently and drive verification clos ure Responsibili tiesThe DV team is expected to:• Own verification of 4–5 design blocks per ASIC• Develop and execute seque nces• Perform test development and d ebug• Drive coverage collection and clo sure• Own end-to-end verification execution for assigned bl ocks• The customer will own the testbench infrastruct ure.
What you’ll do
The engineer will lead the verification of 4–5 ASIC design blocks by developing UVM-based environments, sequences, and tests. They are responsible for driving coverage collection, performing debug, and ensuring end-to-end verification execution for assigned blocks.
Requirements
Candidates must have strong experience in SystemVerilog and UVM verification methodologies. Hands-on expertise with PCIe, UCIe 2.0, or Ethernet protocols is required to independently own and drive design block verification.
Other relevant skills
Identified from the job description. Confirm important requirements above.
- SystemVerilog
- UVM
- PCIe
- UCIe 2.0
- Ethernet
- Design Verification
- ASIC Verification
- Test Development
- Debug
- Coverage Closure
- Sequence Development
Job areas
- Engineering
- Technology
- Software
Additional details
- Minimum experience
- 5+ years
- Posting language
- English
- Working hours
- 40 hours per week
- Seniority
- Mid-Senior level
- Application method
- Direct apply is available