Digital Design Verification Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: The PCIe Subsystem team is seeking a skilled and motivated verification engineer to join our team and to contribute to the success of the projects we are involved in. We are currently looking for an experienced Digital Design Verification engineer, who will be involved in different aspects of verification activities. The candidate will manage/utilize a variety of verification components to ensure the robustness of RTL designs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop and enhance System Verilog/UVM-based testbenches for verifying new and existing PCIe features. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in memory sub-system architecture. Create staging and test plans for new feature development. Effectively testing a design by understanding the functional and performance goals. Take ownership of different verification tasks. Improve productivity through automation using AI tools PREFERRED EXPERIENCE: Architected and developed complex verification environments in UVM, System Verilog. Have personally implemented verification tests, sequences, scoreboards, checkers, assertions and coverage groups. Working experience with PCIe, SATA, Ethernet protocols. Exposure to RTL design, software development, formal verification, or other related domains. Excellent communication, management, and presentation skills. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE/Verdi). Good attention to detail and creative thinking ability. Self-starter and team player with strong analytical skills and independent working ability. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in related discipline preferred. LOCATION: Markham, Ontario, or Vancouver, Canada #LI-MO2 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Develop and enhance System Verilog/UVM-based testbenches to verify PCIe features and ensure RTL design robustness. Collaborate with architects, RTL designers, and performance engineers to create comprehensive test plans and improve productivity through automation.

Requires experience in architecting complex verification environments using UVM and System Verilog. Candidates should have a background in PCIe, SATA, or Ethernet protocols and hold at least a Bachelor's degree in a related discipline.

Identified from the job description. Confirm important requirements above.

• System Verilog
• UVM
• PCIe
• RTL Design
• Verification
• SATA
• Ethernet
• Formal Verification
• VCS
• Debussy
• Verdi
• Processor Architecture
• Automation
• AI Tools
• Debugging
• Testbench Development
• Inventory Staging
• Digital Design
• Self-Starter
• Go-to-Market Strategy
• Responsible AI
• Willingness To Learn
• Analytical Skills
• Artificial Intelligence
• Software Development
• Communication
• Communications Management
• Creative Thinking
• Serial Advanced Technology Attachment (SATA)
• Problem Solving
• PCI Express
• Presentations
• Register-Transfer Level
• Simulations
• Supercomputing
• Systems Architecture
• SystemVerilog (Direct Programming Interface)
• Test Planning
• Detail Oriented

• Engineering
• Technology
• Software
• Design Verification Engineer
• Verification Engineer
• Industrial and Production Engineers
• Electrical Engineers

Minimum education

Bachelor’s degree

Minimum experience

5+ years

Apply by

Jul 31, 2027

Posting language

English

Working hours

40 hours per week