IP Post-Silicon Validation Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The AMD NBIO Team is on the lookout for a dynamic, upbeat IP Validation Design Engineer to join our growing team. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and validation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You are a self-starter with strong analytical and problem-solving skills and are willing to learn and ready to independently drive tasks to completion. KEY RESPONSIBILITIES: As an IP Validation Design Engineer, you will drive the planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs. Defining, documenting, executing and reporting the overall functional test plan and validation strategy for a set of AMD IP’s. Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives. Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs. Engaging on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features. Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives. Developing knowledge of system architecture/debug and other internal IP’s. Supporting issues on customer platforms as requested by customer support teams. PREFERRED EXPERIENCE: Experience in digital logic design/verification/post-silicon validation. Extensive experience with ASIC debug techniques and methodologies. Knowledge of physical and protocol levels of common high-speed interfaces such as PCIe/CXL/UALINK is an asset Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization. Strong scripting skills (eg. Ruby, Python). Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc. In-depth knowledge of PC architectures/PCIe protocol is an asset. Must have excellent written and verbal communication skills. Must excel in a dynamic team working environment. Leadership and mentoring skills are a definite asset. Must be a self-starter and be able to independently drive tasks to completion. ACADEMIC CREDENTIALS: Bachelor’s or master’s degree majoring in EE, CS or related field LOCATION: Markham #LI-TB2 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

The role involves planning, executing, and debugging functional test plans for hardware IP across various AMD SOC programs. It also requires collaborating with cross-functional teams on pre-silicon activities and developing automation tools to enhance validation capabilities.

Candidates should have a degree in EE, CS, or a related field with extensive experience in ASIC debug and digital logic design. Proficiency in scripting languages like Python or Ruby and familiarity with high-speed interfaces like PCIe is highly desired.

Identified from the job description. Confirm important requirements above.

• Post-Silicon Validation
• Digital Logic Design
• ASIC Debugging
• PCIe Protocol
• CXL
• UALink
• Python
• Ruby
• Logic Analyzers
• Oscilloscopes
• System Architecture
• Pre-Silicon Validation
• Hardware IP Validation
• Scripting
• Board-Level Debug
• Digital Verification

• Engineering
• Technology
• Software
• Science & Research
• Manufacturing

Minimum education

Bachelor’s degree

Minimum experience

5+ years

Apply by

Jun 12, 2027

Posting language

English

Working hours

40 hours per week