Semiconductor Packaging Designer/ Senior Package Design Engineer L4 / Principal Package Design Engineer/ Semiconductor Packaging Engineer

Job summary

Perform hands-on semiconductor package design and physical layout using EDA tools while optimizing for power and signal integrity. Coordinate the overall design flow and collaborate with global teams to support multiple PHY test-chip designs annually.

Job details

Title: Semiconductor Packaging Designer/ Senior Package Design Engineer L4 / Principal Package Design Engineer/ Semiconductor Packaging Engineer Duration: 1-year contract-to-hire (open to candidates who only want FTE as well) Location: Ontario - Ottawa or Toronto preferred -Hybrid, 2-3 day's, may be full remote if there is a lack of space in the office. Hours a Week: 40 Start Date: October end or November 1st week Compensation: $65-$70/Hour Interview Process: First interview with Hiring Manager - Virtual Technical panel interview with 2-3 team members - Virtual Day-to-Day Responsibilities: Perform hands-on semiconductor package design and physical layout using computer-based design/EDA tools. Work through package design, modeling, and optimization before progressing into mechanical and thermal modeling. Collaborate during early design stages to define and optimize requirements for power integrity (PI) and signal integrity (SI), including areas such as bump maps. Extract models and analyze package substrate designs. Support approximately 5-7 PHY test-chip package designs per year. Coordinate different phases of the package-design process and overall design flow. Use package-layout/design tools such as Cadence APD, Allegro, Design Force, and AutoCAD. Work with electromagnetic modeling and analysis tools. Troubleshoot complex package-design issues and provide regular project updates to the manager Work with a global engineering team and represent the organization on business-unit projects. Must Haves: 10+ years of relevant design/engineering experience. 5+ years of specific, hands-on semiconductor package-design experience. Strong hands-on physical package layout/design experience. Strong Power Integrity (PI) experience - this is required. Experience with package design/layout tools such as: Cadence APD (highly preferred), Allegro (highly preferred) , Design Force, AutoCAD, Equivalent industry-standard package-design tools may also be considered. Knowledge of 3D electromagnetic modeling tools such as HFSS or similar industry standard tools. Strong understanding of circuit and transmission-line theory. Experience with package model extraction and analysis. Bachelor’s degree in electrical engineering, Electronic Engineering, or equivalent (Bachelor of engineering) Pluses: Strong Signal Integrity (SI) experience - SI can be taught if the candidate has the required PI background. Mechanical and thermal modeling experience. Experience supporting PHY/test-chip package designs. Experience working across both Windows and Linux environments. Career background progressing from: Chip Design → Package Design / Package Operations → Package Design We may use AI-enabled and/or automated tools to support parts of our recruitment process, including application screening, interview scheduling, and candidate communications. These tools are used to enhance consistency and efficiency. All hiring decisions involve human review and are not based solely on automated processing. The Company offers a total rewards package in accordance with all applicable federal, provincial, and local laws and requirements. Benefit eligibility and offerings vary based on role, employment status, and work location. For contractor positions, benefits are limited to those entitlements and protections required by applicable law, which may include (as applicable) vacation pay, public holidays, leaves of absence, and other legally mandated benefits or payments.

What you’ll do

Perform hands-on semiconductor package design and physical layout using EDA tools while optimizing for power and signal integrity. Coordinate the overall design flow and collaborate with global teams to support multiple PHY test-chip designs annually.

Requirements

Requires over 10 years of engineering experience with at least 5 years specifically in semiconductor package design and strong Power Integrity expertise. A Bachelor's degree in Electrical or Electronic Engineering is required.

Listed skills

• AutoCAD · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• Semiconductor Package Design
• Physical Layout
• Power Integrity
• Signal Integrity
• Cadence APD
• Allegro
• Design Force
• AutoCAD
• HFSS
• Electromagnetic Modeling
• Circuit Theory
• Transmission-line Theory
• Package Model Extraction
• Thermal Modeling
• Mechanical Modeling
• PHY Test-chip Design

Job areas

• Engineering
• Technology
• Manufacturing
• Science & Research
• Software