Memory Layout Engineer
The role involves designing and implementing custom layouts for memory blocks such as SRAM, ROM, and TCAM on advanced TSMC FinFET processes. Responsibilities include performing physical verification, resolving IR drop and EM issues, and ensuring seamless top-level memory integration within SoC environments.
- On-site
- Ottawa, ON
- Posted Aug 13, 2026
- Apply by Sep 12, 2026
- 1 position
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Job summary
Job Title: Memory Layout Engineer Location: Ottawa, Ontario, CANADA(Onsite) Fulltime We are looking for a highly skilled Memory Layout Engineer with strong expertise in advanced node technologies to support high-performance semiconductor designs. The ideal candidate will have hands-on experience in memory layout development, physical verification, and top-level integration across SRAM and other memory architectures on TSMC FinFET processes Key Responsibilities • Design and implement custom layouts for memory blocks, including: • SRAM • Register Files • ROM • TCAM • Develop and optimize layouts for critical memory components such as: • Sense amplifiers • Control circuits • I/O blocks • Bit-cell arrays • Decoders • Perform top-level memory integration, ensuring seamless assembly of memory macros within SoC environments • Execute and resolve physical verification checks, including: • DRC (Design Rule Check) • LVS (Layout vs Schematic) • Density checks • Drive layout cleanup and signoff closure, ensuring high-quality tapeout readiness • Analyze and mitigate IR drop and EM (Electromigration) issues in memory layouts • Collaborate with circuit design, physical design, and process teams to ensure optimal performance, area, and power Required Qualifications • Bachelor’s/master’s degree in electrical/Electronic Engineering or related field • Proven experience in memory layout design at advanced technology nodes • Hands-on experience with TSMC 7nm FinFET technology Preferred Qualifications • Experience with TSMC 6nm / 5nm / 4nm / 3nm technologies • Strong understanding of memory architecture and layout methodologies • Familiarity with industry-standard layout and verification tools (e.g., Virtuoso, Calibre) Key Skills • Memory layout design (SRAM, ROM, TCAM, Register Files) • Advanced node layout expertise (FinFET technologies) • Physical verification (DRC, LVS, Density) • IR/EM analysis and mitigation • Top-level memory integration • Strong problem-solving and debugging skills
What you’ll do
The role involves designing and implementing custom layouts for memory blocks such as SRAM, ROM, and TCAM on advanced TSMC FinFET processes. Responsibilities include performing physical verification, resolving IR drop and EM issues, and ensuring seamless top-level memory integration within SoC environments.
Requirements
Candidates must hold a bachelor's or master's degree in Electrical/Electronic Engineering and have proven experience in memory layout design at advanced technology nodes. Hands-on experience with TSMC 7nm FinFET technology is required, with familiarity with 6nm to 3nm nodes preferred.
Listed skills
- Problem solvingPreferred
Other relevant skills
Identified from the job description. Confirm important requirements above.
- Memory Layout Design
- SRAM
- ROM
- TCAM
- Register Files
- FinFET Technologies
- Physical Verification
- DRC
- LVS
- Density Checks
- IR/EM Analysis
- Top-level Memory Integration
- Virtuoso
- Calibre
- Problem-solving
- Debugging
Job areas
- Engineering
- Technology
- Manufacturing
- Science & Research
- Software
Additional details
- Minimum education
- Bachelor’s degree
- Minimum experience
- 5+ years
- Apply by
- Sep 12, 2026
- Posting language
- English
- Working hours
- 40 hours per week
- Seniority
- Entry level
- Application method
- Direct apply is available