Verification Engineer I

We are looking for an experienced Logic / Mixed-Signal Verification Engineer to join on of our premier client's team. Candidates must have experience performing ASIC verification based on architectural and micro-architectural specification review and analysis, followed by definition of verification requirements. The successful candidate will contribute to the verification, timing closure, and validation of complex mixed-signal SoC and ASIC designs, working closely with architecture, RTL, analog, and physical design teams. Responsibilities Verification Planning and Execution Develop verification plans, test strategies, and verification requirements from architectural and micro-architectural specifications. Develop tests and testbench components from high-level verification plans using industry-standard verification methodologies. Define functional coverage goals, implement coverage monitors, analyze coverage results, and drive coverage closure. Execute regressions, debug failing tests, and develop verification collateral to ensure design quality and completeness. Collaborate closely with design and architecture teams to review and refine verification and coverage requirements. Static Timing Analysis (STA) & Design Closure Lead static timing analysis (STA) execution for mixed-signal designs, ensuring robust timing closure across analog-digital interfaces. Develop and maintain timing constraints, timing budgets, and STA methodologies for complex mixed-signal systems. Drive timing optimization activities and collaborate with RTL, analog, and physical design teams to achieve timing closure. Analyze timing reports, identify critical paths, and resolve timing violations throughout the design cycle. Analog Circuit Design & Mixed-Signal Verification Execute analog circuit design and validation tasks, including simulation setup, testbench development, schematic optimization, and performance characterization using Cadence ADE and related tools. Perform comprehensive mixed-signal verification, including analog simulations, behavioral modeling, and timing analysis. Develop and maintain behavioral models to support verification of analog and mixed-signal subsystems. Analyze simulation results to ensure compliance with power, performance, functionality, and reliability requirements. Debug & Problem Resolution Investigate and resolve complex issues in analog testbenches, digital verification environments, and mixed-signal simulations. Perform root-cause analysis of pre-silicon design challenges and implement effective corrective actions. Debug functional, timing, and integration issues across analog and digital domains. Work collaboratively with analog designers, digital architects, RTL engineers, and physical design teams to resolve design and verification challenges. Methodology Development & Automation Advance verification flows, methodologies, and best practices supporting evolving mixed-signal design requirements. Develop automation solutions and productivity tools using scripting languages and emerging AI technologies. Improve simulation efficiency, verification quality, and overall design productivity through methodology enhancements and reusable verification components. Qualifications BSEE, BSCE, or equivalent required; MS preferred. 1-5 years of experience in ASIC logic verification, mixed-signal verification, or related semiconductor design roles. Strong experience with SystemVerilog/Verilog and one or more scripting/programming languages such as Perl, Python, C, or C++. Experience with RTL simulation tools (VCS preferred) and modern verification methodologies. Experience specifying, developing, and debugging functional tests and verification environments. Experience specifying, implementing, and analyzing functional coverage. Practical experience with static timing analysis (STA), timing constraint development, and timing closure methodologies. Familiarity with analog design and simulation environments, including Cadence ADE and mixed-signal verification flows. Strong debug and problem-solving skills with the ability to work across multiple technical disciplines. Excellent interpersonal and communication skills and the ability to work effectively in a highly collaborative global team environment. Experience developing constrained-random test environments is highly desirable. HS diploma or GED equivalent required for US candidates.

The engineer will develop verification plans and testbenches for complex mixed-signal SoC and ASIC designs. They are also responsible for leading static timing analysis and executing analog circuit validation to ensure design quality and timing closure.

Candidates must have a BSEE or BSCE and 1-5 years of experience in ASIC or mixed-signal verification. Proficiency in SystemVerilog, scripting languages, and experience with RTL simulation tools like VCS are required.

• C++Preferred
• PythonPreferred

Identified from the job description. Confirm important requirements above.

• ASIC Verification
• Mixed-Signal Verification
• SystemVerilog
• Verilog
• Static Timing Analysis
• Python
• Perl
• C++
• VCS
• Cadence ADE
• Functional Coverage
• RTL Simulation
• Behavioral Modeling
• Timing Closure
• Constrained-Random Testing
• Analog Circuit Design

• Engineering
• Technology
• Manufacturing
• Software
• Science & Research

Minimum education

High school

Minimum experience

2+ years

Apply by

Sep 10, 2026

Posting language

English

Working hours

40 hours per week

Seniority

Associate

Application method

Direct apply is available