Senior Design Verification Engineer

Job summary

Lead the verification of 4-5 ASIC design blocks by developing UVM-based environments, sequences, and tests. Drive coverage collection and closure while owning end-to-end verification execution for assigned blocks.

Job details

Mandate Skills: Design verification engineers with UVM experience ASIC Programs (Switch/NIC) DV • Lead or contribute to verification of 4–5 ASIC design blocks. • Develop UVM-based verification environments, sequences, tests, debug, and coverage closure. • Strong experience in SystemVerilog/UVM. • Ability to independently own verification deliverables. • Support customer collaboration in EST timezone. Required Skills • Strong SystemVerilog/UVM verification experience. • Ability to own design blocks independently and drive verification closure Responsibilities The DV team is expected to: • Own verification of 4–5 design blocks per ASIC • Develop and execute sequences • Perform test development and debug • Drive coverage collection and closure • Own end-to-end verification execution for assigned blocks • The customer will own the testbench infrastructure.

What you’ll do

Lead the verification of 4-5 ASIC design blocks by developing UVM-based environments, sequences, and tests. Drive coverage collection and closure while owning end-to-end verification execution for assigned blocks.

Requirements

Requires strong experience in SystemVerilog and UVM for ASIC programs such as Switch or NIC. Candidates must be able to independently own verification deliverables and support collaboration in the EST timezone.

Listed skills

• Organization · Preferred
• Collaboration · Preferred
• Attention to detail · Preferred
• Execution · Preferred
• Development · Preferred
• Customer · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• SystemVerilog
• UVM
• ASIC Verification
• Design Verification
• Coverage Closure
• Test Development
• Debug

Job areas

• Engineering
• Technology
• Software