Design Verification Engineer

Job summary

Verify complex ASIC and IP blocks for a combined CPU/GPU development effort, collaborating with design and verification teams to validate functionality at block, chip, and system levels. Document and execute directed and constrained-random simulation tests, and apply evolving verification methodologies within existing project infrastructure.

Job details

Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects. Be familiar with hardware modeling and/or assertion-based verification methods.EXPERIENCE AND EDUCATION: Minimum 5 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;Strong background in C/C++ development in a Linux Environment;Strong debug skills and experience with debug tools such as Gdb, Valgrind;Proficient in Object Oriented programming, STL, computer architecture and data structures;Knowledge of Perl and Makefiles;Experience in Verilog/SystemVerilog/SystemC, preferred;Experience in C/Verilog environment using DPI/PLI, preferred;Strong analytical skills and attention to detail;Excellent written and communication skills. EEO Employer LanceSoft is a certified Minority Business Enterprise (MBE) and an equal opportunity employer. We prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state, or local laws. This policy applies to all employment practices within our organization, including hiring, recruiting, promotion, termination, layoff, recall, leave of absence, compensation, benefits, training, and apprenticeship. LanceSoft makes hiring decisions based solely on qualifications, merit, and business needs at the time.

What you’ll do

Verify complex ASIC and IP blocks for a combined CPU/GPU development effort, collaborating with design and verification teams to validate functionality at block, chip, and system levels. Document and execute directed and constrained-random simulation tests, and apply evolving verification methodologies within existing project infrastructure.

Requirements

Requires at least five years of verification experience on large ASIC projects or software/firmware experience in a hardware development setting, along with strong C/C++ skills in Linux and debugging experience. Also requires proficiency in object-oriented programming, STL, computer architecture, and data structures; Perl and Makefile knowledge, strong analytical and communication skills, and Verilog/SystemVerilog/SystemC and DPI/PLI experience are preferred.

Listed skills

• Verilog · Preferred
• Linux · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• Functional Verification
• ASIC Verification
• IP Core Verification
• C/C++
• Linux
• Debugging
• GDB
• Valgrind
• Object-Oriented Programming
• STL
• Computer Architecture
• Data Structures
• Perl
• Makefiles
• Verilog
• SystemVerilog

Job areas

• Engineering
• Technology
• Software

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