Microchip Technology Inc. is a leading semiconductor supplier of smart, connected and secure embedded control solutions.
Chandler, AZ
Microchip Technology Inc. is a leading semiconductor supplier of smart, connected and secure embedded control solutions. Its easy-to-use development tools and comprehensive product portfolio enable customers to create optimal designs which reduce risk while lowering total system cost and time to market. The company’s solutions serve more than 125,000 customers across the industrial, automotive, consumer, aerospace and defense, communications and computing markets. Headquartered in Chandler, Arizona, Microchip offers outstanding technical support along with dependable delivery and quality. For more information, visit the Microchip website at www.microchip.com. The content on our LinkedIn page may contain AI-generated imagery, performers and/or audio.
On-site · Burnaby
Lead customer platform enablement for PCIe switch products while partnering with hyperscale and storage customers to define technical requirements. Provide advanced technical support, resolve complex system-level issues, and develop high-quality technical collateral for internal and external stakeholders.
On-site · Burnaby
The engineer will design, develop, and execute comprehensive silicon and system validation plans for PCIe switches and NVMe controllers. They will also diagnose complex hardware and software issues while mentoring junior team members in a lab environment.
On-site · Burnaby
The successful candidate will execute chip development methodologies including block-level place and route, physical design verification, and static timing analysis. They will also collaborate across multidisciplinary teams to ensure the successful completion of complex SOCs and ASICs.
On-site · Ottawa
Oversee all aspects of signal and power integrity for device package designs while collaborating with cross-functional teams to meet electrical specifications. Develop and evolve signal integrity flows, perform simulations, and provide models for complex data center and optical communication processors.
On-site · Montréal
Lead the end-to-end software architecture for a next-generation 64-bit RISC-V multi-processor SoC, ensuring compliance with aerospace, defense, and automotive standards. This includes establishing coding standards, mentoring engineering teams, and collaborating with customers and marketing to influence the product roadmap.
On-site · Burnaby
Define the end-to-end software architecture for next-generation 64-bit RISC-V multi-processor SoCs to meet performance and security benchmarks. Lead technical review forums and partner with cross-functional teams to influence product roadmaps and customer success.
On-site · Burnaby
You will characterize, analyze, and debug cutting-edge SERDES architectures while collaborating with mixed-signal designers. Additionally, you will develop automated test platforms, design high-performance hardware, and author technical reports to guide design decisions.
On-site · Burnaby
The ASIC Development Engineer will be responsible for the design, verification, emulation, and validation of digital integrated circuits at various levels. They will work on next-generation storage and memory controller SOC products from initial concept to production.
On-site · Burnaby
You will design, develop, and verify firmware and software components for PCIe switching products while collaborating with cross-functional teams. Additionally, you will lead architecture reviews, mentor junior engineers, and troubleshoot complex issues in both lab and field environments.
On-site · Burnaby
The engineer will enable hardware and firmware development and co-verification of System-On-Chip devices using industry-leading emulators and FPGA platforms. They will collaborate with architects and design teams across all phases of SoC development from architectural exploration to post-silicon validation.
On-site · Burnaby
The Senior SoC Design Engineer will design complex digital integrated circuits at the block, subsystem, or device level using Verilog and System Verilog. They will also collaborate with cross-functional teams to define feature sets, support emulation and lab validation, and communicate design trade-offs to architects.
Remote · Ontario, Canada
The Senior Field Applications Engineer acts as a trusted technical advisor to strategic customers, influencing system architecture and product integration decisions. They partner with sales teams to drive design wins and support customers throughout the entire product lifecycle from concept to production.
On-site · Toronto
Lead customer platform enablement for PCIe switch products and provide advanced technical support for system-level debug and integration. Collaborate with cross-functional teams and customers to ensure successful design, deployment, and production ramp of high-performance data center solutions.
On-site · Toronto
Develop and maintain advanced analysis and transformation passes for high-level synthesis compilers to generate high-performance FPGA designs. Optimize hardware architectures for power, performance, and area while analyzing customer applications to implement new features.
On-site · Toronto
The Product Marketing Manager will own the strategic and tactical marketing for a portfolio of FPGA products, including defining roadmaps and driving go-to-market strategies. They will collaborate with engineering and sales teams to ensure competitive positioning and revenue growth.
On-site · Burnaby
The Senior System Validation Engineer will lead silicon bring-up, system integration, and validation of next-generation SoCs. Responsibilities include developing test infrastructure, executing complex tests, and driving cross-functional debugging across hardware and firmware.
On-site · Burnaby
The Principal System Validation Engineer will lead silicon bring-up, system integration, and validation of next-generation SoCs. This role involves building validation infrastructure, developing test plans, and driving complex debugging across hardware, firmware, and system levels.
On-site · Burnaby
The candidate will own the design planning and construction of pad rings and bump patterns while ensuring alignment with package and system-level constraints. They will also collaborate with cross-functional teams to validate physical design handoff deliverables and support silicon debug efforts.
On-site · Montréal
The candidate will define requirements for mixed-signal IPs and collaborate with SoC architects and IP vendors to customize solutions. They will also manage the full IP integration process and provide post-tape out support, including lab testing and debugging.
On-site · Saskatoon
The Principal Engineer will lead digital design, DFT, physical implementation, and static timing analysis for integrated circuits at block and top-chip levels. They will also collaborate with RTL and DFT teams to ensure correct constraints and deliverables throughout the semiconductor R&D lifecycle.
