Senior Engineer II - Physical Design
- Burnaby, BC
- On-site
- Posted Sep 19, 2026
- 1 position
$86,000–$186,000 / year
Opens an external site
- Employment type
- Full-time
- Experience level
- Senior · 5+ years
- Minimum education
- Bachelor’s degree
- Posting language
- English
- Working hours
- 40 hours per week
Job summary
The successful candidate will execute chip development methodologies including block-level place and route, physical design verification, and static timing analysis. They will also collaborate across multidisciplinary teams to ensure the successful completion of complex SOCs and ASICs.
Job details
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: Microchip is currently looking for a Senior Physical Design Engineer to join our Implementation team in our Burnaby BC office. As a key member of Microchip's Implementation team, the successful candidate will execute chip development methodologies which include block level place and route, physical design verification, macro level test structures, digital wrapper development for analog cells, synthesis, static timing for high-performance devices. The successful candidate will also work closely with our customers to support them through Microchip's Chip development flow, and work with other groups across disciplines (CAD, Packaging, Mixed Signal, Operations, and Design) to ensure the Chip is successfully completed. Our team uses state-of-the-art tools and flows to build large and complex SOCs/ASICs. Requirements/Qualifications: This position requires at least 4-year degree in Electrical or Electronics Engineering with 7.5+ years of ASIC development experience in a fast paced environment. Design, Synthesis, Static Timing and Place & Route experience in high performance design (high speed / low power) is a must. Advanced knowledge of semi-custom design & implementation tools Hands-on experience in all aspects of physical design flows such as floorplanning, placement optimization, clock tree synthesis and physical verification Recent experience with leading full chip Physical Design activities Implement chip level, subsystem, CPU, and mixed signal blocks. Excellent analytical and debugging skills and the ability to proactively solve issues. Ability to guide others based on changing priorities Proven ability to thrive on, learn and adapt to new methodologies and technologies Must be able to work autonomously, but ensure to inform management of current status. Be able to understand Verilog and VHDL languages Excellent oral and written communications skills. Experience with 6nm process or lower a plus Proficiency in Python/PERL/TCL scripting is essential Self-motivated team player that can collaborate with multiple teams across a geographically diverse company to achieve desired design goals is crucial Travel Time: 0% - 25% Pay Range: We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below: Benefits of working at Microchip The annual base salary range for this position is $86,000-$186000.* *Range is dependent on numerous factors including job location, skills and experience. To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
What you’ll do
The successful candidate will execute chip development methodologies including block-level place and route, physical design verification, and static timing analysis. They will also collaborate across multidisciplinary teams to ensure the successful completion of complex SOCs and ASICs.
Requirements
This position requires a bachelor degree in Electrical or Electronics Engineering and over 7.5 years of ASIC development experience. Candidates must possess advanced knowledge of semi-custom design tools and proficiency in scripting languages like Python, Perl, or TCL.
Benefits
- Restricted stock units
- Quarterly bonus payments
- Health benefits
- Retirement savings plans
- IESPP program
Listed skills
- Verilog · Preferred
- VHDL · Preferred
- Python · Preferred
Other relevant skills
Identified from the job description. Confirm important requirements above.
- Asic development
- Physical design
- Place and route
- Synthesis
- Static timing analysis
- Floorplanning
- Placement optimization
- Clock tree synthesis
- Physical verification
- Verilog
- VHDL
- Python
- Perl
- Tcl
- Soc design
- Debugging
- Self-Motivation
- Management
- Decision Making
- Communication
- Training And Development
- Optical Transport Networks
- Empowerment
- Electronic Engineering
- Perl (Programming Language)
- Floor Planning
- Leadership
- Integrated Circuits
- Innovation
- Python (Programming Language)
- Operations
- Restricted Stock
- Static Timing Analysis
- Tcl (Programming Language)
- VHSIC Hardware Description Language (VHDL)
- Writing
- Scripting
- Application Specific Integrated Circuits
- Physical Design
Job areas
- Engineering
- Technology
- Software
- Physical Design Engineer
- Mechanical Design Engineer
- Mechanical Engineers
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