Computer Aided Design Engineer

Job summary

Own and maintain LEC sign-off methodologies across RTL-to-GDS and gate-to-gate flows, and enable safe ECO implementation. Debug equivalence issues, automate verification workflows, optimize tool performance and scalability, and support AI-enabled methodologies in partnership with EDA vendors.

Job details

Job Description: A LEC (Logic Equivalence Checking) CAD Engineer who will develop and support formal equivalence methodologies to ensure functional correctness between RTL, synthesized netlists, and physical designs in complex SoC (System on a Chip) development Key Responsibilities Flow Management: Own and maintain end-to-end LEC sign-off methodologies across RTL-to-GDS and gate-to-gate flows. ECO Implementation: Enable Engineering Change Order (ECO) flows to ensure safe, correct late-stage design modifications. Debugging & Root Cause: Analyze and resolve non-equivalences, aborts, and mismatches across design stages. Automation: Write and maintain scripts and automation infrastructure using Tcl, Python, Perl, or Shell. Tool Optimization: Optimize runtime, capacity, and scalability of verification tools while partnering with EDA vendors. AI Enablement : Enable AI enabled tools and methodologies Core Requirements Tools Knowledge: Proficiency in industry-standard tools like Cadence Conformal (LEC/ECO) and Synopsys Formality. Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or related fields with dedicated hardware/EDA experience

What you’ll do

Own and maintain LEC sign-off methodologies across RTL-to-GDS and gate-to-gate flows, and enable safe ECO implementation. Debug equivalence issues, automate verification workflows, optimize tool performance and scalability, and support AI-enabled methodologies in partnership with EDA vendors.

Requirements

A bachelor's or master's degree in Electrical Engineering, Computer Science, or a related field is required, along with dedicated hardware or EDA experience. Candidates should be proficient with Cadence Conformal and Synopsys Formality and have experience supporting formal equivalence methodologies.

Listed skills

• Root Cause Analysis · Preferred
• Python · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• Logic Equivalence Checking
• Formal Equivalence Verification
• RTL-to-GDS Flows
• Gate-to-Gate Flows
• Engineering Change Orders
• Debugging
• Root Cause Analysis
• Tcl
• Python
• Perl
• Shell Scripting
• Cadence Conformal
• Synopsys Formality
• EDA Tool Optimization
• AI-Enabled Verification

Job areas

• Engineering
• Technology
• Manufacturing

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