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Mirafra Technologies

Verified Job Source

Leader in Product Engineering Sevices

Bangalore, Karnataka

Semiconductor Manufacturing
1,001–5,000 people

About

Mirafra Technologies is a leading Turnkey ASIC Solutions provider and Semiconductor Engineering Services company, helping global technology companies accelerate innovation through end-to-end engineering excellence - from Concept to Silicon to System. With a team of 2,200+ engineers and global delivery centers across India, the United States, Germany (Munich), Taiwan, and Malaysia, Mirafra combines deep domain expertise with a global delivery model to support customers worldwide. As a one-stop engineering partner, we provide end-to-end expertise across the complete semiconductor lifecycle - from architecture, design, verification, physical implementation, package and board design, embedded software, post-silicon validation, test & product engineering, and system solutions. Our engineering excellence is reflected in 650+ tape-out contributions and the trust of 50+ semiconductor customers, ranging from innovative startups to many of the world's leading semiconductor and technology companies. Beyond semiconductor engineering, Mirafra enables customers to build intelligent embedded products and accelerate digital transformation through AI, cloud, data engineering, and scalable software solutions. Driven by engineering excellence, innovation, and customer success, we help customers accelerate time-to-market, reduce engineering complexity, and deliver next-generation semiconductor and intelligent system solutions with confidence.

Open positions

LEC (Logic Equivalence Checking) CAD Engineer

On-site

Own and maintain end-to-end logic equivalence sign-off methodologies across RTL-to-GDS and gate-to-gate flows, and enable safe ECO implementation. Debug non-equivalences, aborts, and mismatches; develop automation scripts; optimize verification tools; and support AI-enabled methodologies.

Computer Aided Design Engineer

On-site

Own and maintain LEC sign-off methodologies across RTL-to-GDS and gate-to-gate flows, and enable safe ECO implementation. Debug equivalence issues, automate verification workflows, optimize tool performance and scalability, and support AI-enabled methodologies in partnership with EDA vendors.

Physical Design Engineer

On-site

Perform timing signoff, constraint validation, multi-corner multi-mode analysis, and timing closure across physical implementation, while analyzing timing, crosstalk, IR drop, and clock-path issues to optimize power, performance, and area. Develop and maintain automated Tcl and Python workflows, use AI-assisted coding tools to improve script development, and establish standardized frameworks, regression tests, and documentation.