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LEC (Logic Equivalence Checking) CAD Engineer

  • ON
  • On-site
  • Posted Oct 17, 2026
  • 1 position

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Employment type
Full-time
Experience level
Senior · 5+ years
Minimum education
Bachelor’s degree
Posting language
English
Working hours
40 hours per week
Seniority
Mid-Senior level
Application method
Apply on LinkedIn (LinkedIn sign-in required)

Job summary

Own and maintain end-to-end logic equivalence sign-off methodologies across RTL-to-GDS and gate-to-gate flows, and enable safe ECO implementation. Debug non-equivalences, aborts, and mismatches; develop automation scripts; optimize verification tools; and support AI-enabled methodologies.

Job details

A LEC (Logic Equivalence Checking) CAD Engineer who will develop and support formal equivalence methodologies to ensure functional correctness between RTL, synthesized netlists, and physical designs in complex SoC (System on a Chip) development Key Responsibilities Flow Management: Own and maintain end-to-end LEC sign-off methodologies across RTL-to-GDS and gate-to-gate flows. ECO Implementation: Enable Engineering Change Order (ECO) flows to ensure safe, correct late-stage design modifications. Debugging & Root Cause: Analyze and resolve non-equivalences, aborts, and mismatches across design stages. Automation: Write and maintain scripts and automation infrastructure using Tcl, Python, Perl, or Shell. Tool Optimization: Optimize runtime, capacity, and scalability of verification tools while partnering with EDA vendors. AI Enablement : Enable AI enabled tools and methodologies Core Requirements Tools Knowledge: Proficiency in industry-standard tools like Cadence Conformal (LEC/ECO) and Synopsys Formality. Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or related fields with dedicated hardware/EDA experience

What you’ll do

Own and maintain end-to-end logic equivalence sign-off methodologies across RTL-to-GDS and gate-to-gate flows, and enable safe ECO implementation. Debug non-equivalences, aborts, and mismatches; develop automation scripts; optimize verification tools; and support AI-enabled methodologies.

Requirements

Requires proficiency with industry-standard formal equivalence tools, including Cadence Conformal and Synopsys Formality. Requires a bachelor's or master's degree in Electrical Engineering, Computer Science, or a related field, along with dedicated hardware or EDA experience.

Listed skills

  • Root Cause Analysis · Preferred
  • Python · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

  • Logic Equivalence Checking
  • Formal Verification
  • RTL-to-GDS Flows
  • Gate-to-Gate Flows
  • ECO Implementation
  • Debugging
  • Root Cause Analysis
  • Tcl
  • Python
  • Perl
  • Shell Scripting
  • Verification Tool Optimization
  • Cadence Conformal
  • Synopsys Formality
  • AI-Enabled Methodologies

Job areas

  • Engineering
  • Technology
  • Manufacturing

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