Physical Design Engineer

Job summary

Perform timing signoff, constraint validation, multi-corner multi-mode analysis, and timing closure across physical implementation, while analyzing timing, crosstalk, IR drop, and clock-path issues to optimize power, performance, and area. Develop and maintain automated Tcl and Python workflows, use AI-assisted coding tools to improve script development, and establish standardized frameworks, regression tests, and documentation.

Job details

Role Overview We are seeking a Physical Design Engineer with a strong foundation in Static Timing Analysis (STA) and a focus on design flow automation. In this role, you will be responsible for driving timing closure across complex, sub-nanometer process nodes while leveraging next-generation development tools. You will play a key role in developing, optimizing, and automating physical design workflows using Tcl and Python, incorporating AI-assisted development tools like GitHub Copilot to accelerate script delivery and engineering efficiency. Key Responsibilities Static Timing Analysis (STA): Execute timing signoff, constraint validation, multi-corner multi-mode (MCMM) analysis, and timing closure across all phases of physical implementation. Flow Automation & Scripting: Write, maintain, and enhance robust automated scripts using Tcl and Python to streamline EDA tool flows (place & route, synthesis, signoff). AI-Assisted Development: Utilize Copilot-assisted development tools to rapidly build, refactor, and test flow automation scripts, optimizing operational productivity. Timing & Power Optimization: Analyze setup/hold violations, crosstalk, IR drop, and clock path issues, collaborating closely with RTL and synthesis teams to achieve optimal PPA (Power, Performance, Area). Process Improvement: Standardize scripting frameworks, build continuous regression tests for physical design tools, and document automated methodologies for the broader team. Qualifications Required Skills & Experience: Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field. Core STA Expertise: In-depth understanding of Static Timing Analysis principles, timing constraints (SDC), clock jitter, skew, cross-talk noise, and signoff methodologies using industry tools (e.g., Synopsys PrimeTime or Cadence Tempus). Scripting Proficiency: Strong hands-on coding ability in Tcl (for EDA tool integration) and Python (for data processing and workflow automation). Modern Development Tooling: Direct experience or strong familiarity with Copilot-assisted coding/script development tools (or LLM-driven coding tools) to write, debug, and optimize scripts efficiently. VLSI Fundamentals: Sound understanding of digital CMOS logic, place and route (PnR) flow fundamentals, and physical verification concepts. Preferred Qualifications: Experience with automated tool API integrations (e.g., Synopsys ICC2/Fusion Compiler, Cadence Innovus APIs). Experience implementing CI/CD pipelines or automated regression frameworks for hardware design flows. Background in Git or modern version control systems for managing Tcl/Python script repositories.

What you’ll do

Perform timing signoff, constraint validation, multi-corner multi-mode analysis, and timing closure across physical implementation, while analyzing timing, crosstalk, IR drop, and clock-path issues to optimize power, performance, and area. Develop and maintain automated Tcl and Python workflows, use AI-assisted coding tools to improve script development, and establish standardized frameworks, regression tests, and documentation.

Requirements

Requires a bachelor’s or master’s degree in electrical engineering, computer engineering, microelectronics, or a related field, along with strong Static Timing Analysis expertise and proficiency in Tcl and Python. Candidates should understand digital CMOS logic, place-and-route flows, and physical verification, and have experience or familiarity with AI-assisted coding tools; experience with EDA APIs, CI/CD or regression frameworks, and Git is preferred.

Listed skills

• Git · Preferred
• Python · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• Static Timing Analysis
• Timing Closure
• Tcl
• Python
• EDA Tool Flow Automation
• Timing Constraint Validation
• MCMM Analysis
• Setup and Hold Analysis
• Power, Performance, and Area Optimization
• Crosstalk Analysis
• IR Drop Analysis
• Place and Route
• Digital CMOS Logic
• Physical Verification
• CI/CD and Regression Testing
• Git

Job areas

• Engineering
• Technology
• Manufacturing

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