CPU Architecture Verification Engineer

Markham, ON
Hybrid
Posted Oct 3, 2026
1 position

US$140,000–US$250,000 / year

Opens an external site

Employment type: Full-time
Experience level: Lead · 10+ years
Minimum education: Bachelor’s degree
Posting language: English
Working hours: 40 hours per week

Job summary

You will drive the verification strategy and test plans to ensure architectural correctness of the CPU against specifications and golden reference models. This involves building robust verification environments, generating stimulus, and collaborating with RTL and architecture teams to root-cause bugs.

Job details

At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove that the Nuvacore CPU is architecturally correct. As part of the design verification (DV) team, you will help drive architectural verification — checking the CPU's behavior and architectural state against the architecture specification and a golden reference model — building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design. THE ROLE * Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness — the CPU's behavior and architectural state versus the specification and a golden reference model. * Environment Setup: Build, maintain, and scale robust verification environments — including co-simulation against the golden reference model — that compare architectural state end to end. * Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions. * Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete. * Cross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up. REQUIREMENTS — MUST TO HAVE * Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience. * 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design. * Strong knowledge of CPU architecture and micro-architecture — the instruction set, architectural state, exceptions, and privilege model — with a good understanding of at least one modern ISA (x86, ARM, or RISC-V). * Hands-on functional verification: test plans, testbenches, checkers, and coverage. * Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus). * Experience writing and debugging tests in assembly for CPU verification. REQUIREMENTS — NICE TO HAVE * Architectural / instruction-set verification against a golden reference model. * Random instruction sequence (RIS) stimulus generation. * Exceptions, interrupts, privilege levels, and virtualization. * Constrained-random verification and coverage-driven closure. * Assertions and formal verification. * Emulation/FPGA and silicon bring-up and debug (waveforms, trace). * * The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up. \n \n $140,000 - $250,000 a year \n

What you’ll do

Requirements

Candidates must have a degree in Electrical/Computer Engineering or Computer Science with extensive experience in CPU design verification. Proficiency in C/C++/Rust, SystemVerilog, and assembly language is required, along with deep knowledge of modern ISA architectures.