NUVACORE is building a new class of CPU for the AI era, designed for maximum performance, efficiency, and scale.
San Jose, California
Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. This is not iteration, it is a complete rewrite of the rules of silicon.
Hybrid · Markham
Architect and deliver high-performance clock generation and distribution networks for CPU cores. Collaborate with cross-functional teams to ensure clock-network closure, including skew, latency, and jitter analysis.
Hybrid · Markham
You will drive the verification strategy and test plans to ensure architectural correctness of the CPU against specifications and golden reference models. This involves building robust verification environments, generating stimulus, and collaborating with RTL and architecture teams to root-cause bugs.
Remote · Canada, India, United States
You will design and own the cycle-accurate CPU performance simulator to drive architectural decisions from pathfinding through post-silicon correlation. You will also lead microarchitectural exploration and collaborate with cross-functional teams to align design implementation with software stack requirements.
Hybrid · Markham
You will drive the formal verification strategy by turning micro-architecture specifications into properties and building robust environments to prove them. Additionally, you will partner with the design team to debug counterexamples and ensure correctness through exhaustive model and equivalence checking.
Hybrid · Markham
You will drive the verification strategy, test plans, and environment development for high-performance CPU designs. Additionally, you will collaborate with architecture and RTL teams to debug complex issues and ensure coverage closure before silicon.
Hybrid · Markham
You will define and implement area and power-efficient DFT architectures while collaborating with design, STA, and PD teams. Additionally, you will be responsible for verification of DFT features, generating test content for silicon bringup, and supporting yield analysis.
