CPU DFT Engineer

Job summary

You will define and implement area and power-efficient DFT architectures while collaborating with design, STA, and PD teams. Additionally, you will be responsible for verification of DFT features, generating test content for silicon bringup, and supporting yield analysis.

Job details

FULL-TIME · MULTIPLE LEVELS · AUSTIN AND SANTA CLARA Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As DFT engineers within the CPU team you will be responsible for test related pre-silicon and post-silicon activities. We will be delivering a DFT architecture which aligns with the projects industry - leading power, performance, and area. THE ROLE As a CPU DFT Engineer, you will participate in the following areas: * Defining and implementing area and power efficient DFT architecture while collaborating with design, STA and PD * Develop scan and BIST insertion flows, implement DFT registers in design blocks * Completing DFT architecture specifications * Review and integrate third party IPs into DFT architecture * Define verification plans for DFT features * Review DFT coverage for scan and MBIST * Verification of DFT features in RTL and gates, and power aware simulations * Generate test content for silicon bringup, and support silicon bringup activities including yield analysis REQUIREMENTS — MUST TO HAVE * BS or MS with 7+ years experience in DFT or DFT verification * Scan or MBIST with industry standard EDA tools, or experience with DFT verification flows * For scan role, able to define scan insertion, scan compression, and clocking requirements, and define intest and extest modes * For MBIST role, be very familiar with memory repair, and repair interaction with functional operation * Strong understanding of JTAG, IEEE 1500 and IEEE 1687 * Experience with Verilog RTL and gate level netlists, including running and debugging simulations * Strong communication skills and ability to work with cross functional teams REQUIREMENTS — NICE TO HAVE * Using DFT features to support system debug * Leveraging AI tools to accelerate DFT work flows * Porting test content and supporting silicon bringup on ATE platforms * Experience in Perl, Python, or TCL * \n \n $140,000 - $250,000 a year \n

What you’ll do

You will define and implement area and power-efficient DFT architectures while collaborating with design, STA, and PD teams. Additionally, you will be responsible for verification of DFT features, generating test content for silicon bringup, and supporting yield analysis.

Requirements

Candidates must have a BS or MS degree with at least 7 years of experience in DFT or DFT verification. Strong proficiency in scan or MBIST flows, industry-standard EDA tools, and RTL/gate-level simulation debugging is required.

Listed skills

• Verilog · Preferred
• Python · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• DFT
• Scan
• MBIST
• Verilog
• RTL
• Gate level netlists
• JTAG
• IEEE 1500
• IEEE 1687
• EDA tools
• Silicon bringup
• Yield analysis
• Perl
• Python
• TCL
• Power aware simulations
• Communication
• Debugging
• Electronic Design Automation
• Perl (Programming Language)
• Joint Test Action (IEEE Standards)
• Python (Programming Language)
• Memory Built-In Self-Tests
• Simulations
• Tcl (Programming Language)
• Yield Management

Job areas

• Engineering
• Technology
• Software
• Dft Engineer
• Integrated Circuit (IC) Design Engineer
• Electronics Engineers
• Computer Hardware Engineers

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