Senior RTL Design Engineer, SoC Subsystems

USD 85 to 110 per hour, roughly USD 170,000 to 220,000 annualized at full utilization, ben…SystemVerilogUVM testbench architectureFunctional and code coverage closureSystemVerilog Assertions (SVA)Constrained random verificationVCS, Xcelium, or QuestaUSD 80 to 120 per hour, approximately USD 160,000 to 240,000 annualized at full utilizatio…SystemVerilog or VHDLVivado or QuartusTiming closure and SDC/XDC constraintsClock domain crossing designPCIe, Ethernet, or DDR interfacesOn chip debug (ILA or Signal Tap)USD 75 to 100 per hour, approximately USD 150,000 to 200,000 annualized at full utilizatio…SystemVerilog RTL designMicroarchitecture specificationLint and CDC signoff (SpyGlass or similar)Synthesis and static timing (Design Compiler or Genus)AMBA AXI, AHB, or APB integrationLow power design intent (UPF)

The role involves designing and verifying SoC subsystems using RTL design and microarchitecture specifications. Responsibilities include ensuring timing closure, managing clock domain crossings, and integrating AMBA interfaces.

Candidates must be proficient in SystemVerilog, UVM, and tools like Vivado or Quartus. Experience with synthesis, static timing analysis, and low power design intent is required.

Identified from the job description. Confirm important requirements above.

• SystemVerilog
• UVM
• RTL Design
• VHDL
• Vivado
• Quartus
• Timing Closure
• SDC/XDC Constraints
• Clock Domain Crossing
• PCIe
• Ethernet
• DDR Interfaces
• AMBA AXI
• AHB
• APB
• UPF

• Engineering
• Technology
• Manufacturing
• Software
• Science & Research

Minimum experience

5+ years

Apply by

Sep 4, 2026

Posting language

English

Working hours

40 hours per week

Seniority

Mid-Senior level