Senior FPGA Design Engineer

Job summary

Design and implement FPGA logic using SystemVerilog, managing the process from micro-architecture through to timing closure. Collaborate with hardware and verification teams to ensure robust designs and improve overall FPGA design methodologies.

Job details

A specialist engineering consultancy supporting ASIC, FPGA, and embedded software development is expanding its team and is looking for a Senior FPGA Design Engineer to join a long-standing client engagement. You will work on-site with a global leader in optical and photonics technology, contributing to advanced, high-speed products at the forefront of optical networking and communications. This is a long-term opportunity for an experienced FPGA engineer who can ramp up quickly, take ownership of complex designs with minimal supervision, and grow into a design prime role over the next couple of years. You will work closely with hardware, verification, and systems teams to take FPGA designs from specification and micro-architecture through implementation and timing closure. This is a full time, onsite position in Ottawa, and you should have full right to work in Canada. Key Responsibilities: Design and implement FPGA logic using SystemVerilog, from micro-architecture through to production-ready, timing-clean designs. Analyze and manage clock domain crossings (CDC), including synchronization strategies and CDC verification. Own the FPGA synthesis flow, including tool configuration, timing constraints, and driving designs through to timing closure. Analyze synthesis and timing reports to identify and resolve timing, congestion, and resource utilization issues. Collaborate closely with hardware, verification, and systems engineering teams to ensure designs are robust, testable, and implementation-friendly. Participate in design reviews and technical documentation. Contribute to improving FPGA design methodologies, processes, and best practices. Take increasing technical ownership with the opportunity to progress toward a design prime position. Key Qualifications: Approximately 10–15 years of hands-on FPGA design experience, with the technical depth to ramp up quickly and take ownership of complex designs. Strong and current expertise in SystemVerilog. Practical experience identifying, analyzing, and resolving clock domain crossing (CDC) challenges. Hands-on experience configuring and managing FPGA synthesis tools. Strong understanding of SDC timing constraints and constraint development. Proven ability to interpret synthesis and timing reports and translate findings into effective design changes. Experience taking FPGA designs through implementation and achieving timing closure. Strong communication and collaboration skills across hardware, verification, and systems teams. Ability and willingness to work full-time on-site in Ottawa, Canada. Legally eligible to work in Canada. Nice to Have: Exposure to UVM-based verification. Scripting experience with Tcl, Python, or similar tools to automate and support FPGA design flows. Familiarity with high-speed interfaces used in optical networking, communications, or photonics products. The role offers a salary of CAD $150,000–$170,000 per year, plus bonus and benefits, with final compensation dependent on experience and technical capability. By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice https://eu-recruit.com/wp-content/uploads/2024/07/European-Tech-Recruit-Privacy-Notice-2024.pdf

What you’ll do

Design and implement FPGA logic using SystemVerilog, managing the process from micro-architecture through to timing closure. Collaborate with hardware and verification teams to ensure robust designs and improve overall FPGA design methodologies.

Requirements

Requires 10-15 years of hands-on FPGA design experience with deep expertise in SystemVerilog and SDC timing constraints. Candidates must be legally eligible to work in Canada and able to work on-site in Ottawa.

Benefits

• Bonus • Benefits

Listed skills

• Python · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• SystemVerilog
• FPGA Design
• Clock Domain Crossing (CDC)
• FPGA Synthesis
• SDC Timing Constraints
• Timing Closure
• Micro-architecture
• UVM
• Tcl
• Python
• Optical Networking
• Photonics

Job areas

• Engineering
• Technology
• Manufacturing
• Consulting
• Software