Design Verification Engineer with UVM

Job summary

Own or contribute to verification for four to five ASIC design blocks, developing and executing UVM-based sequences and tests. Debug issues, drive coverage collection and closure, and manage end-to-end verification for assigned blocks while collaborating with the customer in the EST time zone.

Job details

Must: design verification engineers with UVM, PCIe, UCIe, ethernet verification experience ASIC Programs (Switch/NIC) DV Lead or contribute to verification of 4-5 ASIC design blocks. Develop UVM-based verification environments, sequences, tests, debug, and coverage closure. Strong experience in SystemVerilog/UVM. Experience with PCIe, UCIe 2.0, and Ethernet protocols. Ability to independently own verification deliverables. Support customer collaboration in EST timezone. Required Skills Strong SystemVerilog/UVM verification experience Knowledge and/or hands-on experience with: UCIe 2.0 PCIe Ethernet Ability to own design blocks independently and drive verification closure Responsibilities The DV team is expected to: Own verification of 4-5 design blocks per ASIC Develop and execute sequences Perform test development and debug Drive coverage collection and closure Own end-to-end verification execution for assigned blocks The customer will own the testbench infrastructure.

What you’ll do

Own or contribute to verification for four to five ASIC design blocks, developing and executing UVM-based sequences and tests. Debug issues, drive coverage collection and closure, and manage end-to-end verification for assigned blocks while collaborating with the customer in the EST time zone.

Requirements

Requires strong SystemVerilog and UVM verification experience, along with knowledge or hands-on experience in UCIe 2.0, PCIe, and Ethernet. Candidates must be able to independently own design blocks and drive verification to closure.

Listed skills

• Customer · Preferred
• Time · Preferred
• Collaboration · Preferred
• Development · Preferred
• Execution · Preferred
• Organization · Preferred
• Attention to detail · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• SystemVerilog
• UVM
• ASIC Verification
• PCIe
• UCIe 2.0
• Ethernet
• Verification Environment Development
• Sequence Development
• Test Development
• Debugging
• Coverage Closure
• Design Block Ownership
• End-to-End Verification

Job areas

• Engineering
• Technology
• Software
• Management & Leadership

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