SOC Design Engineer

Job summary

The engineer will define, design, and verify complex ASIC subsystems while collaborating with multi-site teams across the US and India. Responsibilities include developing micro-architecture, implementing RTL, and ensuring design convergence through synthesis and physical design interactions.

Job details

Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Candidate will be responsible for design/developing next generation power control systems. Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, RTL design along with interactions with verification, Synthesis & PD teams for design convergence. Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leads across US and India Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC Design and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed. Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc. Skills/Experience Sr Engineer / Staff Engineer 5 to 8 years of strong experience in digital front end design for ASICs Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl, TCL language Expertise in post-Si debug is a plus Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. Pay range and Other Compensation & Benefits: $129,600.00 - $179,600.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer. If you would like more information about this role, please contact Qualcomm Careers.

What you’ll do

The engineer will define, design, and verify complex ASIC subsystems while collaborating with multi-site teams across the US and India. Responsibilities include developing micro-architecture, implementing RTL, and ensuring design convergence through synthesis and physical design interactions.

Requirements

Candidates must hold a degree in Science or Engineering with at least 5 years of experience in digital front-end ASIC design. Proficiency in RTL coding, low-power methodologies, and familiarity with industry-standard bus protocols and verification tools is required.

Benefits

• Annual discretionary bonus program • Annual RSU grants • Competitive benefits package

Listed skills

• Verilog · Preferred
• VHDL · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• RTL coding
• Verilog
• SystemVerilog
• VHDL
• Low power design
• Clock domain crossing
• Spyglass
• Cadence LEC
• Perl
• Tcl
• AHB
• AXI
• SPMI
• I2C
• SPI
• Post-Si debug
• Product Execution
• Low Power Design
• Design Verification
• Digital Design
• System-on-Chip Development
• REST Assured
• Technology Nodes
• Very-Large-Scale Integration
• Clock Domain Crossing
• Communication
• Data Processing
• Control Systems
• Debugging
• Perl (Programming Language)
• Sales
• Formal Verification
• Front End Design
• Register-Transfer Level
• Simulations
• Tcl (Programming Language)
• VHSIC Hardware Description Language (VHDL)
• Coordinating
• Serial Peripheral Interface
• Application Specific Integrated Circuits

Job areas

• Engineering
• Technology
• Software
• Soc Design Engineer
• Automotive Engineer
• Mechanical Engineers
• Automotive Engineers