CAD Engineer- LEC

Job summary

Develop, automate, and maintain formal equivalence checking flows across ASIC implementation stages, including power-aware verification and ECO validation. Debug complex equivalence issues, optimize verification runtimes, enable EDA tools and scripts, and collaborate with design teams and vendors to support signoff and tape-out readiness.

Job details

Position Overview We are seeking an experienced LEC / Formal Verification CAD Engineer to join our Central CAD & Physical Design Methodology team. In this role, you will be responsible for defining, developing, and maintaining state-of-the-art Formal Equivalence Checking flows across RTL-to-Gate, Gate-to-Gate, and Post-ECO implementation phases. You will work closely with RTL Design, Logic Synthesis, Physical Design, and Low-Power (UPF/CPF) teams to debug complex non-equivalences, optimize verification runtimes, and ensure 100% functional equivalence before mask generation. Key Responsibilities Flow & Methodology Development: Setup, automate, and maintain enterprise-level Logic Equivalence Checking (LEC) flows across all ASIC implementation stages (RTL vs. Synthesized Netlist, Pre-CTS vs. Post-CTS, Post-Route vs. ECO Netlists). Integrate power-aware formal verification checks incorporating UPF (Unified Power Format) / CPF (Common Power Format) for multi-voltage and low-power domains. Debug & Issue Resolution: Root-cause complex non-equivalence issues arising from synthesis optimizations, retiming, clock gating, boundary optimizations, and scan-chain reordering. Debug unmapped points, abort points, and key-point mapping failures in large hierarchical designs. Validate functional correctness of manual and automated Engineering Change Orders (ECOs) (both pre-mask and metal ECOs). CAD & Tool Enablement: Evaluate, benchmark, and deploy industry-standard EDA tools (Cadence Conformal EC, Synopsys Formality). Write Tcl, Python, and Perl scripts to automate flow execution, report generation, and automated debug triage. Collaborate directly with EDA tool vendors to resolve tool bugs, file RAEs/CRs, and drive feature enhancements. Cross-Functional Collaboration: Support front-end RTL, Synthesis, and Physical Design engineers during signoff reviews. Establish signoff criteria and quality metrics for tape-out readiness. Qualifications & Requirements Education & Experience: B.Tech / M.Tech / M.S. in Electrical Engineering, Electronics & Communication, Computer Engineering, or a related VLSI domain. 5+ years of hands-on experience in ASIC CAD, Formal Verification, or Physical Design implementation flows. Technical Expertise: EDA Tools: Expertise in Cadence Conformal EC (LEC/LP) or Synopsys Formality. Languages: Deep knowledge of Verilog, SystemVerilog, and structural netlist syntax. Low-Power Verification: Hands-on experience with UPF / CPF side-file verification (isolation cells, level shifters, power switches). Scripting: Proficient in Tcl, Python, Perl, and Shell scripting for CAD automation. Synthesis & Implementation Knowledge: Strong understanding of logic synthesis concepts (Design Compiler / Genus), DFT insertion, clock tree synthesis (CTS), and place & route (P&R) optimizations.

What you’ll do

Develop, automate, and maintain formal equivalence checking flows across ASIC implementation stages, including power-aware verification and ECO validation. Debug complex equivalence issues, optimize verification runtimes, enable EDA tools and scripts, and collaborate with design teams and vendors to support signoff and tape-out readiness.

Requirements

Requires a B.Tech, M.Tech, or M.S. in electrical engineering, electronics and communication, computer engineering, or a related VLSI field, plus at least five years of relevant experience. Candidates should have expertise in Conformal EC or Formality, Verilog/SystemVerilog, UPF/CPF, scripting, and ASIC synthesis and implementation flows.

Listed skills

• Verilog · Preferred
• Python · Preferred

Other relevant skills

Identified from the job description. Confirm important requirements above.

• Formal Equivalence Checking
• Cadence Conformal EC
• Synopsys Formality
• Verilog
• SystemVerilog
• UPF/CPF Verification
• Tcl
• Python
• Perl
• Shell Scripting
• Logic Synthesis
• DFT Insertion
• Clock Tree Synthesis
• Place and Route
• ECO Validation
• ASIC CAD Automation

Job areas

• Engineering
• Technology
• Manufacturing

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